PIMXRT516SCVM2A datasheet(31/128 Pages) NXP

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Electrical characteristics

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

Set Point #7

Active

• CM7 runs at 200 MHz, lower voltage to 0.9 V;

CM4 is clock gated, lower voltage to 0.9 V

• CM7 domain bus frequency at 100 MHz

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• All peripherals controlled by CM4 core are clock

gated, but remain powered

DCDC_IN

19.7

36.3

VDD_LPSR_IN

28.1

30.7

A

VDD_SNVS_IN

3.7

7.8

A

Total

65.115

119.917

Set Point #9

Active

• CM7 is clock gated, lower voltage to 0.9 V; CM4

runs at 100 MHz, lower voltage to 0.9 V

• CM4 domain bus frequency at 50 MHz

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• All peripherals controlled by CM7 core are clock

gated, but remain powered

DCDC_IN

11.8

27.2

VDD_LPSR_IN

28.3

30.7

A

VDD_SNVS_IN

3.7

7.7

A

Total

39.046

89.887

Set Point #11

Active

• CM7 is power off; CM4 runs at 200 MHz, drive

voltage to 1.0 V

• CM4 domain bus frequency at 100 MHz

• DCDC is off, LDO_LPSR_ANA and

LDO_LPSR_DIG are active

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• The WAKEUPMIX domain, MEGAMIX domain,

and DISPLAYMIX domain are power gated

• All peripherals in LPSRMIX domain are clocked

DCDC_IN

24.2

33.4

A

VDD_LPSR_IN

28.2

31.4

VDD_SNVS_IN

3.7

7.8

A

Total

93.152

103.756

Set Point #12

Active

• CM7 is power off; CM4 runs at 100 MHz, lower

voltage to 0.9 V

• CM4 domain bus frequency at 50 MHz

• DCDC is off, LDO_LPSR_ANA and

LDO_LPSR_DIG are active

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• The WAKEUPMIX domain, MEGAMIX domain,

and DISPLAYMIX domain are power gated

• All peripherals in LPSRMIX domain are clocked

DCDC_IN

24.3

33.1

A

VDD_LPSR_IN

12.3

13.6

VDD_SNVS_IN

3.7

7.6

A

Total

40.682

45.014

Set Point #1

Standby

Suspend

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

2.4

VDD_LPSR_IN

22.3

38.7

A

VDD_SNVS_IN

3.7

7.6

A

Total

8.006

29.853

Table 13. Typical power modes current and power consumption (Dual core) (continued)

PIMXRT516SCVM2A Datasheet(PDF) 31 Page - NXP Semiconductors

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