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PIMXRT516SCVM2A Datasheet(PDF) 98 Page - NXP Semiconductors |
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PIMXRT516SCVM2A Datasheet(HTML) 98 Page - NXP Semiconductors |
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98 / 128 page ![]() i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021 98 NXP Semiconductors Electrical characteristics Figure 48. RMII mode signal timing diagram 4.9.4.3 RGMII signal switching specifications The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver devices. Table 94. RMII signal timing ID Characteristic Min. Max. Unit M16 ENET_CLK pulse width high 35% 65% ENET_CLK period M17 ENET_CLK pulse width low 35% 65% ENET_CLK period M18 ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid 4 — ns M19 ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid — 13 ns M20 ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to ENET_CLK setup 2— ns M21 ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold 2— ns Table 95. RGMII signal switching specifications1 Symbol Description Min. Max. Unit Tcyc 2 Clock cycle duration 7.2 8.8 ns TskewT 3 Data to clock output skew at transmitter -500 500 ps ENET_CLK (input) ENET_TX_EN M16 M17 M18 M19 M20 M21 ENET_RX_DATA[1:0] ENET_TX_DATA (output) ENET_RX_ER ENET_RX_EN (input) |
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