PIMXRT516SCVM2A datasheet(39/128 Pages) NXP

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Electrical characteristics

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

4.2.3.3

LDO_PLL

Table 19 shows the parameters of LDO_PLL.

4.2.3.4

LPSR_LDO_DIG

LPSR_LDO_DIG provides 1.0 V power source (VDD_LPSR_DIG) from 1.8V power domain

(VDD_LPSR_ANA). The trim voltage range of LDO output is from 0.7 V to 1.15 V. There are two work

modes: Low Power mode and High Power mode. In typical PVT case, the static current consumption is

less than 3 A in Low Power mode. The maximum drive strength of this LDO regulator is 50 mA in High

Power mode.

4.2.3.5

LPSR_LDO_ANA

LPSR_LDO_ANA provides 1.8 V power source (VDD_LPSR_ANA) from 3.3 V power domain

(VDD_LPSR_IN). Its default output value is 1.8 V. Two work modes are supported by this LDO: Low

Power mode and High Power mode. In Low Power mode, the LDO provides 2 mA (maximum value) by

consuming only 4 A current. In High Power mode, the LDO provides 75 mA current capacity with 40 A

static power dissipation.

Table 19. LDO_PLL specification

Specification

Min

Typ

Max

Unit

VDDA_1P8_IN

1.71

1.8

1.89

VDDA_1P0

0.9

1.2

I_out

—

External decoupling capacitor

—

2.2

—

F

Table 20. LPSR_LDO_DIG specification

Specification

Min

Typ

Max

Unit

VDD_LPSR_ANA

1.71

1.8

1.89

VDD_LPSR_DIG

0.7

1.15

I_out

—

External decoupling capacitor

—

2.2

—

F

Table 21. LPSR_LDO_ANA specification

Specification

Min

Typ

Max

Unit

VDD_LPSR_IN

3.3

3.6

VDD_LPSR_ANA

—

1.8

—

I_out

—

External decoupling capacitor

—

4.7

—

F

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