PIMXRT516SCVM2A datasheet(86/128 Pages) NXP

86 / 128 page

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

Electrical characteristics

4.9.1

LPSPI timing parameters

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables provide timing

characteristics for classic LPSPI timing modes.

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input

signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.

Figure 35. LPSPI Master mode timing (CPHA = 0)

Table 82. LPSPI Master mode timing

Number

Symbol

Description

Min.

Max.

Units

Note

1fSCK

Frequency of operation

—

fperiph / 2

MHz

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must guaranteed

this limit is not exceeded.

2tSCK

SCK period

2 x tperiph

—ns

2 tperiph = 1000 / fperiph

3tLead

Enable lead time

—

tperiph

—

4tLag

Enable lag time

—

tperiph

—

5tWSCK

Clock (SCK) high or low time

tSCK / 2 - 3

—

6tSU

Data setup time (inputs)

—

7tHI

Data hold time (inputs)

—

8tV

Data valid (after SCK edge)

—

9tHO

Data hold time (outputs)

—

(OUTPUT)

MSB IN

LSB IN

MSB OUT

LSB OUT

(CPOL=0)

SCK

(CPOL=1)

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. If configured as an output.

PCS

(OUTPUT)

SOUT

(OUTPUT)

SIN

(INPUT)

BIT 6 . . . 1

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