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PIMXRT516SCVM2A Datasheet(PDF) 124 Page - NXP Semiconductors |
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PIMXRT516SCVM2A Datasheet(HTML) 124 Page - NXP Semiconductors |
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124 / 128 page ![]() i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021 124 NXP Semiconductors Revision history 7 Revision history Table 115 provides a revision history for this data sheet. Table 115. i.MX RT1170 Data Sheet document revision history (continued) Rev. Number Date Substantive Change(s) Rev. 1 05/2021 • Added 64 KB RAM for CAAM and built-in Manufacturing Protection Hardware in the Section 1.1, Features; removed ECC, tamper protection, and DryICE from the Section 1.1, Features • Updated the SD revision and two new part numbers in the Table 1. Order information • Updated the Figure 1, "Part number nomenclature—i.MX RT11XX family" • Updated the descriptions of Arm, OCRAM, RTC OSC, LPUART, uSHDC, and SNVS in the Table 3. i.MX RT1170 modules list • Updated the CLK1_P/CLK1_N, DCDC_PSWITCH, RTC_XTALI/RTC_XTALO, NC, and POR_B descriptions in the Table 4. Special signal considerations • Updated the Table 9. Electrostatic discharge and latch-up characteristics • Added a comment for VDD_SOC_IN in the Table 11. Operating ranges • Updated the test conditions of Set Point #7 in the Table 14. Typical power modes current and power consumption (Single core) • Updated the Table 15. Typical wakeup time • Updated the DCDC_PSWITCH note in the Section 4.2.1.1, Power-up sequence • Updated the descriptions in the Section 4.2.2, Internal POR and power detect • Updated the comments of output voltage and maximum value of 1.0 V loading output in the Table 22. DCDC characteristics • Updated the clock output range in the Table 27. Arm PLL’s electrical parameters • Updated a typo for 32K frequency in the Section 4.2.6, On-chip oscillators • Added weak pull-up and pull-down parameters in the Table 36. DC specification for GPIO_SNVS bank • Removed the leakage from pad VDD to VSS value and updated the maximum value of input leakage current from Table 37. DC specification for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank • Updated the compliant standards in the Section 4.6.1, MIPI D-PHY electrical characteristics • Added tADCSETUP in the Table 75. ADC electrical specifications (VREFFH = 1.68 V and VADINmax ≤ NVCC_GPIOmax) and Table 76. ADC electrical specifications (1 V ≤ VREFFH < VDD_ANA_18min and VADINmax ≤ VREFH) • Updated the note in the Table 81. Temperature sensor parameters • Removed the Section, SNVS Rev. 0 12/2020 • Initial version |
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