ACE25QC160GLDPTH datasheet(22/73 Pages) ACE

22 / 73 page

ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Configuration and Status Instructions

Write Enable (06H)

See Figure 2, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable Latch

bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register

instruction and Erase/Program Security Registers instruction. The Write Enable instruction sequence: /CS

goes low sending the Write Enable instruction /CS goes high.

Write Disable (04H)

See Figure 3, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable

instruction sequence: /CS goes low -> sending the Write Disable instruction -> /CS goes high. The WEL bit

is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program,

Sector Erase, Block Erase and Chip Erase, Erase/Program Security Registers and Reset instructions.

Figure2. Write Enable Sequence Diagram for SPI Mode (left) or QPI Mode (right)

Figure3. Write Disable Sequence Diagram for SPI Mode (left) or QPI Mode (right)

ACE25QC160GLDPTH Datasheet(PDF) 22 Page - ACE Technology Co., LTD.