ACE25QC160GLDPTH datasheet(24/73 Pages) ACE

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ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Write Status Register (01H or 31H or 11H)

See Figure 5.a (SPI mode) & Figure 5.b (QPI mode), the Write Status Register instruction allows new

values to be written to the Status Register. Before it can be accepted, a Write Enable instruction must

previously have been executed. After the Write Enable instruction has been decoded and executed, the

device sets the Write Enable Latch (WEL).

The Write Status Register instruction has no effect on S23, S20, S19, S18, S17, S16, S15, S1 and S0 of

the Status Register. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched

in. If not, the Write Status Register instruction is not executed. As soon as /CS is driven high, the self-timed

Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in

progress, the Status Register may still be read to check the value of the Write in Progress (WIP) bit. The

Write in Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is

completed. When the cycle is completed, the Write Enable Latch is reset.

The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3,

BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3.

The Write Status Register instruction also allows the user to set or reset the Status Register Protect (SRP1

and SRP0) bits in accordance with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and

SRP0) bits and Write Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The

Write Status Register instruction is not executed once the Hardware Protected Mode is entered.

Figure5 a. Write Status Register Sequence Diagram (SPI mode)

Figure5 b. Write Status Register Sequence Diagram (QPI mode)

ACE25QC160GLDPTH Datasheet(PDF) 24 Page - ACE Technology Co., LTD.