ACE25QC160GLDPTH datasheet(53/73 Pages) ACE

53 / 73 page

ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Quad Page Program (32H)

The Quad Page Program instruction is for programming the memory using for pins: IO0, IO1, IO2 and IO3.

To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable

instruction must previously have been executed to set the Write Enable Latch bit before sending the Page

Program instruction. The Quad Page Program instruction is entered by driving /CS Low, followed by the

command code (32H), three address bytes and at least one data byte on IO pins.

The instruction sequence is shown in Figure 33, .If more than 256 bytes are sent to the device, previously

latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within

the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the

requested addresses without having any effects on the other bytes of the same page. /CS must be driven

high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program

instruction is not executed.

As soon as /CS is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated.

While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of

the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page

Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the

Write Enable Latch bit is reset.A Quad Page Program instruction applied to a page which is protected by

the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 5&6) is not executed

Figure33. Quad Page Program Sequence Diagram (SPI mode only)

ACE25QC160GLDPTH Datasheet(PDF) 53 Page - ACE Technology Co., LTD.