ACE25QC160GLDPTH datasheet(56/73 Pages) ACE

56 / 73 page

ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

32KB Block Erase (52H)

The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction

must previously have been executed to set the Write Enable Latch bit. The 32KB Block Erase instruction is

entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside

the block is a valid address for the 32KB Block Erase instruction. /CS must be driven low for the entire

duration of the sequence.

See Figure 36.a (SPI mode) & Figure 36.b (QPI mode), the 32KB Block Erase instruction sequence: /CS

goes low ->sending 32KB Block Erase instruction ->3-byte address on SI ->/CS goes high. /CS must be

driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block

Erase instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle (whose

duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to

check the value of the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed

Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,

the Write Enable Latch bit is reset. A 32KB Block Erase instruction applied to a block which is protected by

the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 5&6) is not executed.

Figure 36.a. 32KB Block Erase Sequence Diagram (SPI mode)

Figure 36.b. 32KB Block Erase Instruction (QPI Mode)

ACE25QC160GLDPTH Datasheet(PDF) 56 Page - ACE Technology Co., LTD.