ACE25QC160GLDPTH datasheet(27/73 Pages) ACE

27 / 73 page

ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Read Instructions

Read Data (03H)

See Figure 7, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit

being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out

on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is

automatically incremented to the next higher address after each byte of data is shifted out allowing for a

continuous stream of data. This means that the entire memory can be accessed with a single command as

long as the clock continues. The command is completed by driving /CS high. The whole memory can be

read with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an

Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in

progress.

The Read Data (03h) instruction is only supported in Standard SPI mode.

Fast Read (0BH)

See Figure 8.a, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out.

It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising

edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out,

at a Max frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

Figure7. Read Data Bytes Sequence Diagram (SPI Mode only)

Figure8 a. Fast Read Sequence Diagram (SPI Mode)

ACE25QC160GLDPTH Datasheet(PDF) 27 Page - ACE Technology Co., LTD.