ACE25QC160GLDPTH datasheet(51/73 Pages) ACE

51 / 73 page

ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Program and Erase Instructions

Page Program (02H)

The Page Program instruction is for programming the memory. A Write Enable instruction must previously

have been executed to set the Write Enable Latch bit before sending the Page Program instruction.

See Figure 32.a (SPI mode) & Figure 32.b (QPI mode), the Page Program instruction is entered by driving

/CS Low, followed by the instruction code, 3-byte address and at least one data byte on SI. If the 8 least

significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current

page are programmed from the start address of the same page (from the address whose 8 least significant

bits (A7-A0) are all zero). /CS must be driven low for the entire duration of the sequence. The Page

Program instruction sequence: /CS goes low-> sending Page Program instruction ->3-byte address on SI

->at least 1 byte data on SI-> /CS goes high.

If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data

bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are

sent to device, they are correctly programmed at the requested addresses without having any effects on

the other bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been

latched in; otherwise the Page Program instruction is not executed.

As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While

the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in

Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0

when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is

reset.

A Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,

BP0) bits (see Table 5&6) is not executed.

ACE25QC160GLDPTH Datasheet(PDF) 51 Page - ACE Technology Co., LTD.