AM79C978AVCW datasheet(30/256 Pages) AMD

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Am79C978A

Figure 1.

Media Independent Interface

MII Receive Interface

The MII receive clock is also generated by the external

PHY and is sent to the Am79C978A controller on the

RX_CLK input pin. The clock will be the same fre-

quency as the TX_CLK but will be out of phase and can

run at 25 MHz or 2.5 MHz, depending on the speed of

the network to which the external PHY is attached.

The RX_CLK is a continuous clock during the reception

of the frame, but can be stopped for up to two RX_CLK

periods at the beginning and the end of frames, so that

the external PHY can sync up to the network data traffic

necessary to recover the receive clock. During this

time, the external PHY may switch to the TX_CLK to

maintain a stable clock on the receive interface. The

Am79C978A controller will handle this situation with no

loss of data. The data is a nibble-wide (4 bits) data

pa th, RXD (3:0 ), from the exter n al PHY to th e

Am79C978A controller and is synchronous to the rising

edge of RX_CLK.

The receive process starts when RX_DV is asserted.

RX_DV will remain asserted until the end of the receive

frame. The Am79C978A controller requires CRS (Carrier

Sense) to toggle in between frames in order to receive

them properly. Errors in the currently received frame are

signaled across the MII by the RX_ER pin. RX_ER can be

used to signal special conditions out of band when RX_DV

is not asserted. Two defined out-of-band conditions for this

are the 100BASE-TX signaling of bad Start of Frame De-

limiter and the 100BASE-T4 indication of illegal code group

before the receiver has synched to the incoming data. The

Am79C978A controller will not respond to these condi-

tions. All out of band conditions are currently treated as

NULL events. Certain in band non-IEEE 802.3u-compliant

flow control sequences may cause erratic behavior for the

Am79C978A controller.

MII Network Status Interface

The MII also provides signals that are consistent and

necessary for IEEE 802.3 and IEEE 802.3u operation.

These signals are CRS (Carrier Sense) and COL (Col-

lision Sense). Carrier Sense is used to detect non-idle

activity on the network. Collision Sense is used to indi-

cate that simultaneous transmission has occurred in a

half-duplex network.

MII Management Interface

The MII provides a two-wire management interface so

that the Am79C978A controller can control and receive

status from external PHY devices.

The Network Port Manager copies the PHYAD after

the Am79C978A controller reads the EEPROM and

uses it to communicate with the external PHY. The

PHY address must be programmed into the EEPROM

prior to starting the Am79C978A controller. This is

necessary so that the internal management controller

can work autonomously from the software driver and

can always know where to access the external PHY.

The Am79C978A controller is unique by offering di-

rect hardware support of the external PHY device

without software support. The PHY address of 1Fh is

reserved and should not be used. To access the ex-

ternal PHYs, the software driver must have knowl-

edge of the external PHY’s address when multiple

PHYs are present before attempting to address it.

The MII Management Interface uses the MII Control, Ad-

dress, and Data registers (BCR32, 33, 34) to control and

communicate to the external PHYs. The Am79C978A

controller generates MII management frames to the ex-

ternal PHY through the MDIO pin synchronous to the ris-

ing edge of the Management Data Clock (MDC) based on

a combination of writes and reads to these registers.

RXD(3:0)

RX_DV

RX_ER

RX_CLK

TXD(3:0)

TX_EN

Am79C978A

COL

CRS

Receive Signals

Transmit Signals

Management Port Signals

Network Status Signals

TX_CLK

MDIO

MDC

22399A-4

AM79C978AVCW Datasheet(PDF) 30 Page - Advanced Micro Devices

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