AM79C978AVCW datasheet(61/256 Pages) AMD

61 / 256 page

Am79C978A

Am79C978A controller will poll the next TDTE. If the

transmit descriptor OWN bit has a 0 value, the

Am79C978A controller will resume incrementing the

poll time counter. If the transmit descriptor OWN bit has

a value of 1, the Am79C978A controller will begin filling

the FIFO with transmit data and initiate a transmission.

This end-of-operation poll coupled with the TDTE loo-

kahead operation allows the Am79C978A controller to

avoid inserting poll time counts between successive

transmit frames.

By default, whenever the Am79C978A controller

completes a transmit frame (either with or without

error) and writes the status information to the cur-

rent descriptor, then the TINT bit of CSR0 is set to

indicate the completion of a transmission. This

causes an interrupt signal if the IENA bit of CSR0

has been set and the TINTM bit of CSR3 is cleared.

TheAm79C978A controller provides two modes to

reduce the number of transmit interrupts. The inter-

rupt of a successfully transmitted frame can be sup-

pressed by setting TINTOKD (CSR5, bit 15) to 1.

Ano t her m ode , whic h is en ab l ed b y s e tti ng

LTINTEN (CSR5, bit 14) to 1, allows suppression of

interrupts for successful transmissions for all but

the last frame in a sequence.

Receive Descriptor Table Entry

If the Am79C978A controller does not own both the

current and the next Receive Descriptor Table Entry

(RDTE), then the Am79C978A controller will continue

to poll according to the polling sequence described

above. If the receive descriptor ring length is one, then

there is no next descriptor to be polled.

If a poll operation has revealed that the current and the

next RDTE belong to the Am79C978A controller, then

additional poll accesses are not necessary. Future poll

operations will not include RDTE accesses as long as

the Am79C978A controller retains ownership of the

current and the next RDTE.

When receive activity is present on the channel, the

Am79C978A controller waits for the complete address

of the message to arrive. It then decides whether to ac-

cept or reject the frame based on all active addressing

schemes. If the frame is accepted, the Am79C978A

controller checks the current receive buffer status reg-

ister CRST (CSR41) to determine the ownership of the

current buffer.

If ownership is lacking, the Am79C978A controller will

immediately perform a final poll of the current RDTE.

If ownership is still denied, the Am79C978A controller

has no buffer in which to store the incoming message.

The MISS bit will be set in CSR0 and the Missed

Frame Counter (CSR112) will be incremented. An-

other poll of the current RDTE will not occur until the

frame has finished.

If the Am79C978A controller sees that the last poll (ei-

ther a normal poll, or the final effort described in the

above paragraph) of the current RDTE shows valid

ownership, it proceeds to a poll of the next RDTE. Fol-

lowing this poll, and regardless of the outcome of this

poll, transfers of receive data from the FIFO may begin.

Regardless of ownership of the second receive de-

scriptor, the Am79C978A controller will continue to per-

form receive data DMA transfers to the first buffer. If the

frame length exceeds the length of the first buffer, and

the Am79C978A controller does not own the second

buffer, ownership of the current descriptor will be

passed back to the system by writing a 0 to the OWN

bit of RMD1. Status will be written indicating buffer

(BUFF = 1) and possibly overflow (OFLO = 1) errors.

If the frame length exceeds the length of the first (cur-

rent) buffer, and the Am79C978A controller does own

the second (next) buffer, ownership will be passed

back to the system by writing a 0 to the OWN bit of

RMD1 when the first buffer is full. The OWN bit is the

only bit modified in the descriptor. Receive data trans-

fers to the second buffer may occur before the

Am79C978A controller proceeds to look ahead to the

ownership of the third buffer. Such action will depend

upon the state of the FIFO when the OWN bit has been

updated in the first descriptor. In any case, lookahead

will be performed to the third buffer and the information

gathered will be stored in the chip, regardless of the

state of the ownership bit.

This activity continues until the Am79C978A controller

recognizes the completion of the frame (the last byte of

this receive message has been removed from the

FIFO). TheAm79C978A controller will subsequently

update the current RDTE status with the end of frame

(ENP) indication set, write the message byte count

(MCNT) for the entire frame into RMD2, and overwrite

the “current” entries in the CSRs with the “next” entries.

Receive Frame Queuing

The Am79C978A controller suppor ts the lack of

RDTEs when SRAM (SRAM SIZE in BCR 25, bits 7-0)

is enabled through the Receive Frame Queuing mech-

anism. When the S R A M SIZ E = 0, t hen the

Am79C978A controller reverts back to the PCnet-PCI

II mode of operation. This operation is automatic and

does not require any programming by the host. When

SRAM is enabled, the Receive Frame Queuing mech-

anism allows a slow protocol to manage more frames

without the high frame loss rate normally attributed to

FIFO-based network controllers.

The Am79C978A controller will store the incoming

frames in the extended FIFOs until polling takes place,

if enabled and it discovers it owns an RDTE. The stored

frames are not altered in any way until written out into

system buffers. When the receive FIFO overflows, fur-

ther incoming receive frames will be missed during that

AM79C978AVCW Datasheet(PDF) 61 Page - Advanced Micro Devices

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