AM79C978AVCW datasheet(59/256 Pages) AMD

59 / 256 page

Am79C978A

Figure 34.

32-Bit Software Model

Polling

If there is no network channel activity and there is no

pre- or post-receive or pre- or post-transmit activity

being performed by the Am79C978A controller, then

the Am79C978A controller will periodically poll the cur-

rent receive and transmit descriptor entries in order to

ascertain their ownership. If the DPOLL bit in CSR4 is

set, then the transmit polling function is disabled.

A typical polling operation consists of the following se-

quence. TheAm79C978A controller will use the current

receive descriptor address stored internally to vector to

the appropriate Receive Descriptor Table Entry

(RDTE). It will then use the current transmit descriptor

address (stored internally) to vector to the appropriate

Transmit Descriptor Table Entry (TDTE). The accesses

will be made in the following order: RMD1, then RMD0

of the current RDTE during one bus arbitration, and

after that, TMD1, then TMD0 of the current TDTE dur-

ing a second bus arbitration. All information collected

during polling activity will be stored internally in the ap-

propriate CSRs, if the OWN bit is set (i.e., CSR18,

CSR19, CSR20, CSR21, CSR40, CSR42, CSR50,

CSR52).

A typical receive poll is the product of the following

conditions:

1. The controller does not own the current RDTE and

the poll time has elapsed and RXON = 1 (CSR0,

bit 5), or

2. The controller does not own the next RDTE and

there is more than one receive descriptor in the ring

and the poll time has elapsed and RXON = 1.

If RXON is cleared to 0, the Am79C978A controller will

never poll RDTE locations.

In order to avoid missing frames, the system should

have at least one RDTE available. To minimize poll ac-

tivity, two RDTEs should be available. In this case, the

poll operation will only consist of the check of the status

of the current TDTE.

Initialization

Block

CSR1

CSR2

RMD

Rcv Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

RMD

TMD0

TMD1 TMD2 TMD3

Xmt Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16]

IADR[15:0]

TLE RES RLE RES

MODE

PADR[47:32]

RES

LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Rcv

Buffers

Xmt

Buffers

22399A-37

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