AM79C978AVCW datasheet(37/256 Pages) AMD

37 / 256 page

Am79C978A

Figure 8.

Disconnect of Slave Cycle When Busy

Figure 9.

Disconnect of Slave Burst Transfer - No

Host Wait States

Figure 10.

Disconnect of Slave Burst Transfer -

Host Inserts Wait States

Parity Error Response

When the Am79C978A controller is not the current bus

master, it samples the AD[31:0], C/BE[3:0], and the

PAR lines during the address phase of any PCI com-

mand for a parity error. When it detects an address par-

ity error, the Am79C978A controller sets PERR (PCI

Status register, bit 15) to 1. When reporting of that error

is enabled by setting SERREN (PCI Command regis-

ter, bit 8) and PERREN (PCI Command register, bit 6)

to 1, the Am79C978A controller also drives the SERR

signal low for one clock cycle and sets SERR (PCI Sta-

tus register, bit 14) to 1. The assertion of SERR follows

the addr ess phas e b y t w o cl ock c ycles. T h e

Am79C978A controller will not assert DEVSEL for a

PCI transaction that has an address parity error when

PERREN and SERREN are set to 1. See Figure 11.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

CMD

PAR

DATA

ADDR

22399A-11

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

PAR

DATA

1st DATA

22399A-12

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

23456

PAR

DATA

1st DATA

22399A-13

AM79C978AVCW Datasheet(PDF) 37 Page - Advanced Micro Devices

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