AM79C978AVCW datasheet(40/256 Pages) AMD

40 / 256 page

Am79C978A

Am79C978A controller supports zero wait state read

cycles. It asserts IRDY immediately after the address

phase and at the same time starts sampling DEVSEL.

Figure 14 shows two non-burst read transactions. The

first transaction has zero wait states. In the second

transaction, the target extends the cycle by asserting

TRDY one clock later.

Basic Burst Read Transfer

The Am79C978A controller supports burst mode for

all bus master read operations. The burst mode

must be enabled by setting BREADE (BCR18, bit

6). To allow burst transfers in descriptor read oper-

ations, the Am79C978A controller must also be pro-

grammed to use SWSTYLE 3 (BCR20, bits 7-0). All

burst read accesses to the initialization block and

descriptor ring are of the PCI command type Mem-

ory Read (type 6). Burst read accesses to the trans-

mit buffer typically are longer than two data phases.

When MEMCMD (BCR18, bit 9) is cleared to 0, all

burst read accesses to the transmit buffer are of the

PCI command type Memory Read Line (type 14).

When MEMCMD (BCR18, bit 9) is set to 1, all burst

read accesses to the transmit buffer are of the PCI

command type Memory Read Multiple (type 12).

AD[1:0] will both be 0 during the address phase in-

dicating a linear burst order. Note that during a

burst read operation, all byte lanes will always be

active. The Am79C978A controller will internally

discard unneeded bytes.

The Am79C978A controller will always perform only a

single burst read transaction per bus mastership pe-

riod, where transaction is defined as one address

ph as e an d o n e or mul t i p l e da ta p h a s es. T h e

Am79C978A controller supports zero wait state read

cycles. It asserts IRDY immediately after the address

phase and at the same time starts sampling DEVSEL.

FRAME is deasserted when the next to last data phase

is completed.

Figure 15 shows a typical burst read access. The

Am79C978A controller arbitrates for the bus, is

granted access, reads three 32-bit words (DWord)

from the system memory, and then releases the bus.

In the example, the memory system extends the data

phase of each access by one wait state. The exam-

ple assumes that EXTREQ (BCR18, bit 8) is cleared

to 0, therefore, REQ is deasserted in the same cycle

as FRAME is asserted.

Figure 14.

Non-Burst Read Transfer

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0110

PAR

2345678

DATA

ADDR

DATA

PAR

0000

0110

0000

22399A-17

AM79C978AVCW Datasheet(PDF) 40 Page - Advanced Micro Devices

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