TUSB6250 datasheet(92/124 Pages) TI

92 / 124 page

ATA/ATAPI Interface Port

11−11

SLLS535A − January 2004

TUSB6250

11.5.2

ATPIFCNFG1: ATA/ATAPI Interface Configuration Register 1 (XDATA at F0D1)

543

ATP_MOD

SOFT_RST

HARD_RST

XFER_DIR

AUTO_CMD

START_ATAPI

NON_DA_CMD

DEV_SEL

R/W

W/C

R/W

W/C

R/W

BIT

NAME

RESET

FUNCTION

DEV_SEL

ATAPI device select.

When ATP_MOD = 1 and AUTO_CMD =1 and START_ATAPI =1, and,

DEV_SEL = 0 The internal state machine sets the DEV bit of the device/head register to 0 when

it sends the packet command.

DEV_SEL = 1 The internal state machine sets the DEV bit of the device/head register to 1 when

it sends the packet command.

NON_DA_CMD

Non-data command.

When START_ATAPI = 1, and,

NON_DA_CMD = 0 The internal state machine expects to transfer data between the TUSB6250

and the storage device.

NON_DA_CMD = 1 The internal state machine does not transfer data.

START_ATAPI

Start ATA/ATAPI transfer. Set by the MCU/self-clear.

When this bit is set (START_ATAPI = 1), the internal state machine starts:

S Sending a command if AUTO_CMD = 1, or,

S Transferring data if AUTO_CMD = 0.

START_ATAPI remains active for one clock cycle. It is cleared thereafter automatically.

The data transfer size is determined by the transfer byte count TRNS_BCN [31:0].

AUTO_CMD

Auto command.

When this bit is set (AUTO_CMD = 1), the internal state machine automatically fetches the CBW

command and command parameters from Task_File0 to Task_File15, which is loaded to the

storage device to start the command execution once the MCU sets START_ATAPI to 1.

XFER_DIR

ATA/ATAPI data transfer direction.

XFER_DIR = 0 Data transfer is from the host (TUSB6250) to the storage device.

XFER_DIR = 1 Data transfer is from the storage device to the host (TUSB6250).

HARD_RST

ATA/ATAPI hardware reset. Set and cleared by the MCU.

When this bit is set (HARD_RST = 1), the TUSB6250 drives the RST_ATA pin low, which creates

a hard reset to the storage device. To dismiss a hard reset to the storage device, the MCU needs

to write a 0 to the HARD_RST bit.

SOFT_RST

ATA/ATAPI state machine soft reset. Set by the MCU/self cleared.

When this bit is set (SOFT_RST = 1), the internal logic generates a soft reset to:

S Reset the internal state machines,

S Reset sector FIFO pointers (to 0),

S Clear the internal data buffer.

The internal soft reset signal lasts one clock cycle. The SOFT_RST bit is automatically cleared

to 0, thereafter. The SOFT_RST bit has nothing to do with any reset function to the ATA/ATAPI

device.

ATP_MOD

ATAPI mode.

ATP_MOD = 0 The storage device utilizes ATA transfer protocol.

ATP_MOD = 1 The storage device utilizes ATAPI transfer protocol.

TUSB6250 Datasheet(PDF) 92 Page - Texas Instruments

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