TUSB6250 datasheet(98/124 Pages) TI

98 / 124 page

ATA/ATAPI Interface Port

11−17

SLLS535A − January 2004

TUSB6250

The recovery time is defined in the unit of 60-MHz clock cycle (16.67 ns), which reflects the tK parameter (for

multiword DMA) or tRP parameter (for ultra DMA) value in an actual ATA/ATAPI drive (see the ATA/ATAPI-5

specification, page 294 and 300).

The TUSB6250 state machine automatically adds extra clock cycle(s) to the recovery time setup value based

on the DMA mode used:

•

Multiword DMA: two extra clock cycle;

•

Ultra DMA: one extra clock cycle.

Therefore, a 0−31 value in the DMASPRC register is corresponding to 2−33 clock cycles of multiword DMA

transfer recovery time or 1−32 clock cycles of ultra DMA transfer recovery time.

The TUSB6250 has a fixed two 60-MHz clock cycle (33.34 ns) write data hold time for multiword DMA write

data transfer, which is part of the additional two extra clock cycle recovery time mentioned above.

765

43210

RSV

DRCVT4

DRCVT3

DRCVT2

DRCVT1

DRCVT0

R/O

R/W

BIT

NAME

RESET

FUNCTION

4−0

DRCVT [4:0]

00h

DMA transfer speed (recovery time) in the unit of 60-MHz clock cycle.

7−5

RSV

000

Reserved

11.5.16 Data Transfer Mode and Timing Reference Chart

The TUSB6250 firmware builds a default lookup table based on the correlation data between the data transfer

modes and their corresponding timing given in Table 11−4 through Table 11−6. It should be noted that the

assertion and recovery time given here does not reflect the actual performance of the TUSB6250 ATA/ATAPI

data transfer engine. The intention of listing these timings is to provide a set of timing values that complies

with the ATA/ATAPI-5 specification requirement. End product vendors can develop their custom firmware with

different timing settings to be adapted to the actual performance of their drive. The timing below is based on

the 60-MHz clock (using 16 ns as a typical clock cycle period) that the ATA/ATAPI controller state machine

is running.

Table 11−4. PIO Mode and Timing Correlation Chart

CYCLE TIME (t0)

ASSERTION TIME (t2)

RECOVERY TIME (t2I)

PIO

TRANSFER

MODE

TIME

(ns)

TIME

(ns)

# OF CLKS (SEE

NOTE 1)

TIME

(ns)

# OF CLKS (SEE

NOTE 1)

TRANSFER

MODE

SPEC

(MIN)

ACTUAL

SPEC

(MIN)

ACTUAL

SETTING

ACTUAL

SPEC

(MIN)

ACTUAL

SETTING

ACTUAL

600

600.12

290

300.06

N/A

300.06

383

383.41

290

300.06

N/A

83.35

330

333.4

290

300.06

N/A

33.34

180

183.37

83.35

100.02

120

133.36

83.35

50.01

Other

N/A

600.12

N/A

300.06

N/A

300.06

NOTES:

1. All the actual timing listed is based on the 60-MHz clock cycle (16.67 ns) used in the TUSB6250.

2. The spec value listed is based on the ATA/ATAPI-5 specification.

3. The actual assertion time is obtained based on the consideration that both the register and data transfer timings have to be met.

4. The actual recovery time is obtained with the consideration to meet both the cycle time and the recovery time value specified in the

ATA/ATAPI-5 specification, after meeting the assertion time.

5. Since the TUSB6250 hardware always adds one extra clock cycle to the assertion time value and two extra clock cycles to the

recovery time value, the TUSB6250 firmware needs to use one less than the desired number of clock cycles for any assertion time

and two less for any recovery time programming value. For example, to achieve 300.06-ns assertion and recovery time for PIO mode

0, instead of using 18 clock cycles as the assertion and recovery time value, the TUSB6250 firmware only needs to use 17 clock

cycles as assertion time and 16 clock cycles as the recovery time programming value.

6. According to the ATA/ATAPI-5 specification, the TUSB6250 firmware can issue an IDENTIFY DEVICE command to determine the

supported modes of the mass storage device and then use the corresponding timing in this table during the data transfer.

TUSB6250 Datasheet(PDF) 98 Page - Texas Instruments

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