MPC8308CVMADDA datasheet(44/95 Pages) NXP

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4

13 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC/SDIO) interface

of the MPC8308.

The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the

SD_DAT[0:3]/CMD as outputs and rising edge to sample the SD_DAT[0:3], CMD, CD and WP as inputs.

This behavior is true for both full and high speed modes.

13.1

eSDHC DC Electrical Characteristics

This table provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device,

compatible with SDHC specifications. The eSDHC NVDD range is between 3.0 V and 3.6 V.

Table 38. eSDHC interface DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

VOH

IOH = –8.0 mA

2.4

—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

LCLK

UPM Mode Input Signal:

LUPWAIT

tLBIXKH

tLBIVKH

tLBIXKH

tLBKHOZ

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:3]/LWE

tLBKHOV

tLBKHOZ

Input Signals:

LD[0:15]

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