MPC8308CVMADDA datasheet(8/95 Pages) NXP

8 / 95 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

RESET initialization

Table 9. RTC_PIT_CLOCK AC Timing Specifications

RESET initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the device.

5.1

RESET DC electrical characteristics

This table provides the DC electrical characteristics for the RESET pins.

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter/

Symbol

Min

Typ

Max

Unit

Notes

SYS_CLK_IN frequency

fSYS_CLK_IN

—

66.67

MHz

1, 6

SYS_CLK_IN period

tSYS_CLK_IN

—

41.67

—

SYS_CLK_IN rise and fall time

tKH, tKL

0.6

1.2

SYS_CLK_IN duty cycle

tKHK/tSYS_CLK_IN

—

SYS_CLK_IN jitter

—

±150

4, 5

Notes:

Caution: The system and core must not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for SYS_CLK_IN are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread @ 33 kHz (max rate).

Parameter/

Symbol

Min

Typ

Max

Unit

Notes

RTC_PIT_CLOCK frequency

fRTC_PIT_CLOCK

32768

—

RTC_PIT_CLOCK rise and fall time

tRTCH, tRTCL

1.5

—

s—

RTC_PIT_CLOCK duty cycle

tRTCHK/tRTC_PIT_CLO

—

Table 10. RESET Pins DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

VIH

—2.0

NVDD +0.3

Input low voltage

VIL

—–0.3

0.8

Input current

IIN

0 V

 V

IN NVDD

±5

A

Output high voltage

VOH

IOH = –8.0 mA

2.4

—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

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