MPC8308CVMADDA datasheet(47/95 Pages) NXP

47 / 95 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

13.2.2

Full Speed Input Path (Read)

This figure provides the data and command input timing diagram.

Figure 36. Full Speed Input Path

13.3

eSDHC AC Timing Specifications

This table provides the eSDHC AC timing specifications.

Table 40. eSDHC AC Timing Specifications for High Speed Mode

At recommended operating conditions NVDD = 3.3 V ± 300 mV.

Parameter

Symbol 1

Min

Max

Unit

Notes

SD_CLK clock frequency—high speed mode

fSHSCK

050

MHz

SD_CLK clock cycle

tSHSCK

—

SD_CLK clock frequency—identification mode

fSIDCK

0400

kHz

—

SD_CLK clock low time

tSHSCKL

7—

SD_CLK clock high time

tSHSCKH

7—

SD_CLK clock rise and fall times

tSHSCKR/

tSHSCKF

—3

Input setup times: SD_CMD, SD_DATx

tSHSIVKH

3—

Input hold times: SD_CMD, SD_DATx

tSHSIXKH

2—

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

tSHSKHOV

3—

Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid

tSHSKHOX

–3

—

SD Card Input Setup

tISU

6—

SD Card Input Hold

tIH

2—

tCLK_DELAY

Output from the

SD CLK at

the Card Pin

SD Card Pins

tSFSIVKH

tSFSIXKH

Driving

Edge

Sampling

Edge

tOH

tDATA_DELAY

tODLY

tSFSCK (Clock Cycle)

(MPC8308 Input Hold)

SD CLK at the

MPC8308 Pin

Input at the

MPC8308 Pins

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