MPC8308CVMADDA datasheet(9/95 Pages) NXP

9 / 95 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

RESET initialization

5.2

RESET AC electrical characteristics

This table provides the reset initialization AC timing specifications.

This table provides the PLL lock times.

Table 11. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET (input) to activate reset flow

—

tSYS_CLK_IN

Required assertion time of PORESET with stable power and clock applied to

SYS_CLK_IN

—

tSYS_CLK_IN

—

HRESET assertion (output)

512

—

tSYS_CLK_IN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with

respect to negation of PORESET

4—

tSYS_CLK_IN

—

Input hold time for POR configuration signals with respect to negation of HRESET

0—

—

Time for the device to turn off POR configuration signal drivers with respect to the

assertion of HRESET

—4

Time for the device to turn on POR configuration signal drivers with respect to the

negation of HRESET

1—

1, 2

Notes:

1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN.

2. POR configuration signals consists of CFG_RESET_SOURCE[0:3].

Table 12. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Note

System PLL lock time

—

100

s—

e300 core PLL lock time

—

100

s—

MPC8308CVMADDA Datasheet(PDF) 9 Page - NXP Semiconductors

MPC8308CVMADDA Datasheet(HTML) 9 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Datasheet Download

Link URL