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SH79F024XU Datasheet(PDF) 27 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU Datasheet(HTML) 27 Page - SINOWEALTH Electronic Ltd |
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27 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 27 7.6. 7.6. 7.6. 7.6.4 4 4 4 Port Port Port Port Share Share Share Share The 22 bi-directional I/O ports can also share second or third special function. But the share priority should obey the Outer Outer Outer Outer Most Most Most Most Inner Inner Inner Inner Lest Lest Lest Lest rule: The out most pin function in Pin Pin Pin Pin Configuration Configuration Configuration Configuration has the highest priority, and the inner most pin function has the lowest priority. This means when one pin is occupied by a higher priority function (if enabled), it cannot be used as the lower priority functional pin , even the lower priority function is also enabled. Only until the higher priority function is closed by hardware or software, can the corresponding pin be released for the lower priority function use. Also the function that need pull up resister is also controlled by the same rule. When port share function is enabled, the user can modify PxCR, PxPCR (x = 0-3), but these operations will have no effect on the port status until the second function was disabled. When port share function is enabled, any read or write operation to port will only affect the data register while the port pin keeps unchanged until all the share functions are disabled. PORT0 PORT0 PORT0 PORT0:::: - OPOUT (P0.0): OP output - CMP (P0.1): CMP negative input - AN0-AN4 (P0.2 - P0.6): ADC input channel - VREF (P0.5): ADC reference voltage input Table Table Table Table 7 7 7 7....17 17 17 17 Port 0 Share Table Pin Pin Pin Pin No. No. No. No. Priority Priority Priority Priority Function Function Function Function Enable Enable Enable Enable bit bit bit bit 24 1 OPOUT Set AMPEN AMPEN AMPEN AMPEN bit in CURSAMP CURSAMP CURSAMP CURSAMP Register 2 P0.0 Clear AMPEN AMPEN AMPEN AMPEN bit in CURSAMP CURSAMP CURSAMP CURSAMP Register 23 1 CMP Set CMPEN CMPEN CMPEN CMPEN bit in CURSAMP CURSAMP CURSAMP CURSAMP Register 2 P0.1 Clear CMPEN CMPEN CMPEN CMPEN bit in CURSAMP CURSAMP CURSAMP CURSAMP Register 20-22 18 1 AN0-AN2 AN4 Set CH0 CH0 CH0 CH0,,,, CH1 CH1 CH1 CH1,,,, CH2 CH2 CH2 CH2,,,, CH4 CH4 CH4 CH4 bit in ADCH ADCH ADCH ADCH Register 2 P0.2-P0.4 P0.6 Clear CH0 CH0 CH0 CH0,,,, CH1 CH1 CH1 CH1,,,, CH2 CH2 CH2 CH2,,,, CH4 CH4 CH4 CH4 bit in ADCH ADCH ADCH ADCH Register 19 1 VREF Set REFC REFC REFC REFC bit in ADCON ADCON ADCON ADCON Register 2 AN3 Clear REFC REFC REFC REFC bit in ADCON ADCON ADCON ADCON Register, set CH3 CH3 CH3 CH3 bit in ADCH ADCH ADCH ADCH Register 3 P0.5 Clear REFC REFC REFC REFC bit in ADCON ADCON ADCON ADCON Register, clear CH3 CH3 CH3 CH3 bit in ADCH ADCH ADCH ADCH Register |
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