SH79F024XU datasheet(41/92 Pages) SINOWEALTH

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SH79F

SH79F082

082

7.8.8

7.8.8 External

External

External Interrupt

Interrupt

Interrupt IIIInputs

nputs

The SH79F082 has 3 external interrupt inputs. External interrupt0-1 each has one vector address. External interrupt 4 has 2

inputs; all of them share one vector address. These external interrupts can be programmed to be level-triggered or edge-

triggered by clearing or setting bit IT1 or IT0 in register TCON and register EXF1. If ITn = 0 (n = 0-1), external interrupt 0/1 is

triggered by a low level detected at the INT0/1 pin. If ITn = 1 (n = 0-1), external interrupt 0/1 is edge triggered. In this mode if

consecutive samples of the INT0/1 pin show a high level in one cycle and a low level in the next cycle, interrupt request flag

in register EXF1 is set, causing an interrupt request. Since the external interrupt pins are sampled once each machine cycle,

an input high or low level should be held for at least one machine cycle to ensure proper sampling.

If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine cycle,

and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request

flag is set. Notice that IE0-1 is automatically cleared by CPU when the service routine is called while IF4x should be cleared

by software. External interrupt4 operates in the similar ways except have different registers and have more selection of

trigger.

If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is

generated, which will take 2 machine cycles. If the external interrupt is still asserted when the interrupt service routine is

completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEx (x = 0, 1) when the interrupt is

level sensitive, it simply tracks the input pin level.

If an external interrupt is enabled when the SH79F082 is put into Power down or Idle mode, the interrupt occurrence will

cause the processor to wake up and resume operation.

Note

: IE0-1 is automatically cleared by CPU when the service routine is called while IF40-41 should be cleared by software.

>1 machine Cycle

High-Level Threshold

Low-Level Threshold

7.8.

7.8.9

9 Interrupt

Interrupt

Interrupt Summary

Summary

Source

Vector

Address

Enable

Enable bits

bits

Flag

Flag bits

bits

Polling

Polling Priority

Priority

Interrupt

Interrupt number

number

(c lang

lang

language

uage

uage))))

Reset

0000H

0 (higest)

INT0

0003H

EX0

IE0

Timer0

000BH

ET0

TF0

INT1

0013H

EX1

IE1

Timer1

001BH

ET1

TF1

EUART

0023H

RI+TI

ADC

0033H

EADC

ADCIF

INT4

0053H

EX4+IENC

IF4X

PWM

0063H

EPWM+PWMP/1/2IE

PWMP/1/2IF

FAULT

006BH

EFLT

FLTF

SH79F024XU Datasheet(PDF) 41 Page - SINOWEALTH Electronic Ltd

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