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SH79F024XU Datasheet(PDF) 13 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU Datasheet(HTML) 13 Page - SINOWEALTH Electronic Ltd |
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13 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 13 7. 7. 7. 7. Normal Normal Normal Normal Function Function Function Function 7.1 7.1 7.1 7.1 CPU CPU CPU CPU 7.1.1 7.1.1 7.1.1 7.1.1 C C C CPU PU PU PU Core Core Core Core SFR SFR SFR SFR Feature Feature Feature Feature � CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator Accumulator Accumulator Accumulator ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the Accumulator simply as A. B B B B Register Register Register Register The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register. Stack Stack Stack Stack Pointer Pointer Pointer Pointer (SP) (SP) (SP) (SP) The Stack Pointer Register is 8 bits wide, It is incremented before data is stored during PUSH，CALL executions and it is decremented after data is out of stack during POP, RET, RETI executions. The stack may reside anywhere in on-chip internal RAM (00H-FFH). On reset, the Stack Pointer is initialized to 07H causing the stack to begin at location 08H. Program Program Program Program Status Status Status Status Word Word Word Word Register Register Register Register (PSW) (PSW) (PSW) (PSW) The PSW register contains program status information. Table Table Table Table 7 7 7 7....1 1 1 1 PSW Register Data Data Data Data Pointer Pointer Pointer Pointer Register Register Register Register ((((DPTR DPTR DPTR DPTR)))) DPTR consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address, but it may be manipulated as a 16-bit register or as two independent 8-bit registers. D0H D0H D0H D0H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 PSW PSW PSW PSW C AC F0 RS1 RS0 OV F1 P R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 0 0 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7 7 7 7 C C C C Carry Carry Carry Carry flag flag flag flag b b b bit it it it 0: no carry or borrow in an arithmetic or logic operation 1: a carry or borrow in an arithmetic or logic operation 6 6 6 6 AC AC AC AC Auxiliary Auxiliary Auxiliary Auxiliary Carry Carry Carry Carry flag flag flag flag b b b bit it it it 0: an auxiliary carry or borrow in an arithmetic or logic operation 1: an auxiliary carry or borrow in an arithmetic or logic operation 5 5 5 5 F0 F0 F0 F0 F0 F0 F0 F0 flag flag flag flag bit bit bit bit Available to the user for general purposes 4-3 4-3 4-3 4-3 RS[1:0] RS[1:0] RS[1:0] RS[1:0] R0-R7 R0-R7 R0-R7 R0-R7 Register Register Register Register bank bank bank bank select select select select bits bits bits bits 00: Bank 0 (Address to 00H-07H) 01: Bank 1 (Address to 08H-0FH) 10: Bank 2 (Address to 10H-17H) 11: Bank 3 (Address to 18H-1FH) 2 2 2 2 OV OV OV OV Overflow Overflow Overflow Overflow flag flag flag flag bit bit bit bit 0: no overflow happen 1: an overflow happen 1 1 1 1 F F F F1 1 1 1 F F F F1 1 1 1 flag flag flag flag bit bit bit bit Available to the user for general purposes 0 0 0 0 P P P P Parity Parity Parity Parity flag flag flag flag bit bit bit bit 0: an even number of ``one'' bits in the Accumulator 1: an odd number of ``one'' bits in the Accumulator |
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