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SH79F024XU Datasheet(PDF) 46 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU Datasheet(HTML) 46 Page - SINOWEALTH Electronic Ltd |
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46 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 46 8.1.5 8.1.5 8.1.5 8.1.5 PWM PWM PWM PWM Period Period Period Period and and and and Duty Duty Duty Duty In the PWM module, there are one 12 bits Period register and three 12 bits duty registers; these registers are used to set PWM frequency and duty cycle individually. Table Table Table Table 8 8 8 8....5 5 5 5 PWM Period Control Register 0 (PWMPL) Table Table Table Table 8 8 8 8....6 6 6 6 PWM Period Control Register (PWMPH) Notes: Notes: Notes: Notes: 1. In edge-aligned mode, PWM output period cycle = [PP11, PP.0] X PWM clock. In center-aligned mode, PWM output period cycle = 2 X [PP11, PP.0] X PWM clock. 2. If Period Register = 0x000, Duty over flow interrupt and Period overflow interrupt will not occurs, PWM1/2 outputs inactive level and PWM11/21 output active level regardless of PWM duty cycle. 3. When writing these two register, low byte should be written first then write high byte, because high byte writing operation will copy these two register to really counter, only change low byte is useless. Table Table Table Table 8 8 8 8....7 7 7 7 PWM1/11 Duty Control Register0 (PWM1DL) Table Table Table Table 8 8 8 8....8 8 8 8 PWM1/11 Duty Control Register1 (PWM1DH) DA DA DA DAH H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 PWMPL PWMPL PWMPL PWMPL PP.7 PP.6 PP.5 PP.4 PP.3 PP.2 PP.1 PP.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 0 0 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7 7 7 7-0 -0 -0 -0 PP.7 PP.7 PP.7 PP.7----PP.0 PP.0 PP.0 PP.0 PWM period register low 8 bits DB DB DB DBH H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 PWMPH PWMPH PWMPH PWMPH - - - - PP.11 PP.10 PP.9 PP.8 R/W R/W R/W R/W - - - - R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) - - - - 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 3-0 3-0 3-0 3-0 PP. PP. PP. PP.11- 11- 11- 11-PP. PP. PP. PP.8 8 8 8 PWM period register high4 bits DE DE DE DEH H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 PWM1DL PWM1DL PWM1DL PWM1DL PD1.7 PD1.6 PD1.5 PD1.4 PD1.3 PD1.2 PD1.1 PD1.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 0 0 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7-0 7-0 7-0 7-0 PD PD PD PD1 1 1 1[7:0] [7:0] [7:0] [7:0] PWM1/11 duty register low 8 bits 0DF 0DF 0DF 0DFH H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 PWM PWM PWM PWM1 1 1 1DH DH DH DH - - - - PD1.11 PD1.10 PD1.9 PD1.8 R/W R/W R/W R/W - - - - R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) - - - - 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 3-0 3-0 3-0 3-0 PD PD PD PD1 1 1 1[11 [11 [11 [11::::8 8 8 8]]]] PWM1/11 duty register high 4 bits |
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