SPC574S60 datasheet(62/77 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Sx

62/77

DS10601 Rev 6

4tSDC CC D SCK duty cycle(4)

SCK drive strength

Very strong

0pF

1/2tSCK -2

1/2tSCK +2 ns

PCS strobe timing

5tPCSC CC D

PCSx to PCSS

time(5)

PCS and PCSS drive strength

Very strong

25 pF

—ns

6tPASC CC D

PCSS to PCSx

time(5)

PCS and PCSS drive strength

Very strong

25 pF

—ns

SIN setup time

7tSUI

CC D

SIN setup time to

SCK(6)

SCK drive strength

Very strong

25 pF

—

SIN hold time

8tHI

CC D

SIN hold time from

SCK(6)

SCK drive strength

Very strong

0pF

—

SOUT data valid time (after SCK edge)

9tSUO CC D

SOUT data valid

time from SCK(7)

SOUT and SCK drive strength

Very strong

25 pF

—

5ns

SOUT data hold time (after SCK edge)

tHO

CC D

SOUT data hold

time after SCK(7)

SOUT and SCK drive strength

Very strong

25 pF

—

1. Protocol clock is 40 MHz and all pads are configured as very strong.

2. All timing values for output signals in this table are measured to 50% of the output voltage.

3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may

cause incorrect operation.

4. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

5. PCSx and PCSS using same pad configuration.

6. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

Table 40. DSPI CMOS master classic timing (full duplex and output only) –

MTFE = 0(1) (continued)

Symbol

Characteristic

Condition

Value(2)

Unit

Pad drive(3)

Load (CL)Min

Max

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