SPC574S60 datasheet(42/77 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Sx

42/77

DS10601 Rev 6

3.11.5

Power management electrical characteristics

3.12

PMU monitor specifications

3.12.1

Nomenclature

•

POR stands for Power On Reset. The POR circuit manages the reset from very low

voltage up to its threshold. Cannot be disabled.

•

MVD stands for Minimum Voltage Detector. It cannot be disabled by the user and

generate a destructive Reset.

•

LVD stands for Low Voltage Detector. It can be disabled by the user.

•

HVD stands for High Voltage Detector. It can be disabled by the user.

•

UVD stands for Upper Voltage Detector. It cannot be disabled by the user and generate

a destructive reset.

Table 24. Voltage regulator electrical characteristics(1)

Symbol

Parameter

Conditions(2)

Value(3)

Unit

Min

Typ

Max

CREG

Internal voltage regulator stability

external capacitance

—1.1

2.2(4)

2.97

µF

RDECREGn SR

Stability capacitor equivalent serial

resistance

Total resistance including

board track

1—

CV1V2

EMC cap to be placed on every

1.2 V pin

VDD/VSS pair

100

135

CDECBV

SR Decoupling capacitance ballast

VDD_BV/VSS_LV pair

1.1

2.2(4)

2.97

µF

VMREG

CC Main regulator output voltage

Before trimming

1.21

1.27

1.32(5)

After trimming

1.22

1.25

1.28

IDDMREG

Main regulator current provided to

VDD_LV domain

—

300

ΔIDDMREG SR Main regulator current variation

20 µs observation window

-100

—

100

1. All 1.2V pins should be shorted externally on board with minimum resistance and minimum inductance. It is recommended

to use a 1.2V plane on which all 1.2V pins are shorted to keep resistance and inductance negligible. Recommended

capacitors should be placed very close to the device pins such that parasitic resistance can be reduced. Connection from

VDD_LV pin to capacitor top plate should not exceed more than 5mohm in resistance and 0.5nH in inductance. Similarly

connection from bottom plate of capacitor to PCB ground should not have more than 5mohm resistance and 0.5nH

inductance.

2. VDD = 5.0 V ± 10%, TA = -40 / 125 °C, unless otherwise specified.

3. All values need to be confirmed during device validation.

4. Recommended X7R or X5R ceramic -43% / +35% variation, 20% tolerance and 12.5% temperature.

5. At power-up condition before trimming.

SPC574S60 Datasheet(PDF) 42 Page - STMicroelectronics

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