SPC574S60 datasheet(65/77 Pages) STMICROELECTRONICS

65 / 77 page

DS10601 Rev 6

65/77

SPC574Sx

Electrical characteristics

Figure 23. DSPI CMOS master mode – modified timing, CPHA = 0

SOUT data hold time (after SCK edge)

tHO

CC D

SOUT data hold

time after SCK

SOUT and SCK drive strength

Very strong

25 pF

—

1. Protocol clock is 40 MHz and all pads are configured as very strong.

2. All timing values for output signals in this table are measured to 50% of the output voltage.

3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may

cause incorrect operation.

4. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

5. PCSx and PCSS using same pad configuration.

Table 41. DSPI CMOS master modified timing (full duplex and output only) –

MTFE = 1(1) (continued)

Symbol

Characteristic

Condition

Value(2)

Unit

Pad drive(3)

Load (CL)Min

Max

Data

Last Data

First Data

Data

Last Data

SIN

SOUT

PCSx

SCK Output

(CPOL = 0)

(CPOL = 1)

tSCK

tSDC

tCSC

tASC

tSUI

tHI

tSUO

tHO

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