SPC574S60 datasheet(10/77 Pages) STMICROELECTRONICS

10 / 77 page

Introduction

SPC574Sx

10/77

DS10601 Rev 6

Deserial serial peripheral

interface (DSPI)

Provides a synchronous serial interface for communication with external

devices

Direct Memory Access (DMA)

Performs complex data transfers with minimal intervention from a host

processor via 32 programmable channels.

DMACHMUX

Allows to route a defined number of DMA peripheral sources to the DMA

channels

Flash memory

Provides non-volatile storage for program code, constants and variables

Frequency-modulated phase

locked loop (PLL0)

Output independent of core clock frequency

Frequency-modulated phase-

locked loop (PLL1)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC)

Provides priority-based preemptive scheduling of interrupt requests

PBRIDGE

System bus to peripheral bus interface

RAM controller

Acts as an interface between the system bus and the integrated system RAM

System RAM

Supports read/write accesses mapped to the SRAM memory from any master

Flash memory controller

Acts as an interface between the system bus and the Flash memory module

Flash memory

Up to 1.5 M of programmable, non-volatile Flash memory for code and 32 KB

for data

IRCOSC

Controls the internal 16 MHz RC oscillator system

XOSC

Controls the on-chip oscillator (XOSC) and provides the register interface for the

programmable features

JTAG Master

Provides software the option to write data for driving JTAG

JTAG Data Communication

Module (JDC)

Provides the capability to move register data between the IPS and JTAG

domains

PASS

Programs a set of Flash memory access protections, based on user

programmable passwords

Sequence Processing Unit (SPU) Provides on-device trigger functions similar to those found on a logic analyzer

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Mode entry module (MC_ME)

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control

unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

MC_PMC

Contains registers that enable/disable the various voltage monitors

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the

device

Memory protection unit (MPU)

Provides hardware access control for all memory references generated in a

device

Table 3. SPC574Sx series block summary (continued)

Block

Function

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