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LPC86X Datasheet(PDF) 49 Page - NXP Semiconductors |
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LPC86X Datasheet(HTML) 49 Page - NXP Semiconductors |
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49 / 99 page ![]() LPC86x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2023. All rights reserved. Product data sheet Rev.3 — 28 April 2023 49 of 97 NXP Semiconductors LPC86x 32-bit Arm Cortex-M0+ microcontroller [3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [4] FRO enabled; system oscillator disabled; system PLL disabled. [5] BOD disabled. [6] All peripherals are disabled in the SYSAHBCLKCTRL register. Peripheral clocks disabled in system configuration block. [7] All oscillators and analog blocks are turned off. [8] WAKEUP pin pulled HIGH externally. [9] Tested in production, VDD = 3.3 V. Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 14. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD aaa-027455 -40 -10 20 50 80 110 220 240 260 280 300 320 Temp (°C) IDD DD IDD (μA) (μA) (μA) 1.8V 1.8V 1.8V 2V 2V 2V 2.4V 2.4V 2.4V 2.7V 2.7V 2.7V 3.3V 3.3V 3.3V 3.6V 3.6V 3.6V |
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