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WM8599SEFT/V Datasheet(PDF) 52 Page - Wolfson Microelectronics plc |
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WM8599SEFT/V Datasheet(HTML) 52 Page - Wolfson Microelectronics plc |
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52 / 74 page ![]() WM8599 Product Preview w PP Rev 1.0 January 2007 52 Figure 32 R14 – ADC Control Register 2 Figure 33 R15 – ADC Control Register 3 R14 (0Eh) – ADC Control Register 2 (ADC_CTRL2) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 0 0 0 Write N/A N/A N/A N/A N/A N/A N/A N/A Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read 0 0 Write N/A N/A ADC_BCLKDIV[2:0] ADC_SR[2:0] Default 0 0 0 0 0 0 0 0 N/A = Not Applicable (no function implemented) Function Description ADC_SR[2:0] ADC MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = Reserved ADC_BCLKDIV[2:0] ADC BCLK Rate (when ADC in Master Mode) 000 = MCLK / 4 001 = MCLK / 8 010 = 32fs 011 = 64fs 100 = 128fs All other values of ADC_BCLKDIV[2:0] are reserved R15 (0Fh) – ADC Control Register 3 (ADC_CTRL3) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 0 0 0 Write N/A N/A N/A N/A N/A N/A N/A N/A Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 Write N/A N/A N/A N/A N/A N/A N/A ADC_MSTR Default 0 0 0 0 0 0 0 0 N/A = Not Applicable (no function implemented) Function Description ADC_MSTR ADC Master Mode Select 0 = Slave mode, ADCBCLK and ADCLRCLK are inputs to WM8599 1 = Master mode, ADCBCLK and ADCLRCLK are outputs from WM8599 |
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