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WM8599SEFT/V Datasheet(PDF) 17 Page - Wolfson Microelectronics plc |
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WM8599SEFT/V Datasheet(HTML) 17 Page - Wolfson Microelectronics plc |
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17 / 74 page  Product Preview WM8599 w PP Rev 1.0 January 2007 17 Figure 7 2-wire Read Protocol AUTO-INCREMENT REGISTER READBACK It is possible to read from multiple consecutive registers in continuous readback mode. Continuous readback mode is selected by setting AUTO_INC. In continuous readback mode, the WM8599 will return the indexed register first, followed by consecutive registers in increasing index order until the controller issues a stop sequence. Figure 8 2-Wire Auto-Increment Register Readback REGISTER RESET Any write to register R0 (00h) will reset the WM8599. All register bits are reset to their default values. DEVICE ID AND REVISION Reading from register R0 returns the device ID. Reading from register R1 returns the device revision number. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 DEVICE_ID 00h 15:0 DEVICE_ID [15:0] 10000101 10011001 Device ID A read of this register will return the device ID, 0x8599. R1 REVISION 01h 7:0 REVNUM [7:0] N/A Device Revision A read of this register will return the device revision number. This number is sequentially incremented if the device design is updated. Table 6 Device ID and Revision Number GLOBAL ENABLE CONTROL The WM8599 includes a number of enable and disable mechanisms to allow the device to be powered on and off in a pop-free manner. A global enable control bit enables the ADC, DAC and analogue paths. For full details of pop-free operation, see ‘Pop and Click Performance’ on page 40. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12 ENABLE 0Ch 0 GLOBAL_ EN 0 Device Global Enable 0 = ADC, DAC and PGA ramp control circuitry disabled 1 = ADC, DAC and PGA ramp control circuitry enabled Table 7 Global Enable Control |
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