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WM8599SEFT/V Datasheet(PDF) 15 Page - Wolfson Microelectronics plc |
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WM8599SEFT/V Datasheet(HTML) 15 Page - Wolfson Microelectronics plc |
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15 / 74 page ![]() Product Preview WM8599 w PP Rev 1.0 January 2007 15 DEVICE DESCRIPTION INTRODUCTION The WM8599 is a high performance multi-channel audio CODEC with 2Vrms line level inputs and outputs and flexible analogue input / output switching. The device comprises a 24-bit stereo ADC, two 24-bit stereo DACs with independent digital volume control, and a flexible analogue input and output multiplexer. Analogue inputs and outputs are all at 2Vrms line level, minimising external component count. The DACs share left/right clocks, bit clocks and master clocks with independent data inputs. The ADC uses a separate left/right clock, bit clock and master clock, allowing independent recording and playback in audio applications. The ADC audio interface can be configured to operate in either master or slave clocking mode. In master mode, left/right clocks and bit clocks are all outputs. In slave mode, left/right clocks and bit clocks are all inputs. The DAC audio interface is configured to operate in slave mode. The ADC includes digital gain control, allowing signals to be gained and attenuated between +30dB and -97dB in 0.5dB steps. The DACs include independent digital volume control, which is adjustable between +12dB and - 100dB in 0.5dB steps. The DACs can be configured to output stereo audio data and a range of mono audio options. The input multiplexer accepts five stereo line level inputs at up to 2Vrms. One stereo input can be routed to the ADC, and all five stereo inputs can be routed to the output multiplexer. The output multiplexer includes analogue volume control with zero cross, adjustable between +6dB and -73.5dB in 0.5dB steps, and configurable soft ramp rate. Analogue audio is output at 2Vrms line level. Control of the internal functionality of the device is by 2-wire serial control interface with readback. The interface may be asynchronous to the audio data interface as control data will be re- synchronised to the audio processing internally. In addition, control of mute, power-down and reset may also be achieved by pin selection. Operation using system clocks of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided. ADC and DACs may be clocked independently. Sampling rates from 32kHz to 192kHz are supported for both DACs provided the appropriate master clock is input. Sampling rates from 32kHz to 96kHz are supported for the ADC provided the appropriate master clock is input. The audio data interface supports right justified, left justified, and I 2S interface formats along with a highly flexible DSP serial port interface format. CONTROL INTERFACE Control of the WM8599 is achieved by a 2-wire SM-bus-compliant serial interface with readback. Many devices can be controlled by the same bus, and each device has a unique 7-bit address. REGISTER WRITE The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address and read/write bit, MSB first). If the device address received matches the address of the WM8599, the WM8599 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised, the WM8599 returns to the idle condition and waits for a new start condition with valid address. When the WM8599 has acknowledged a correct address, the controller sends the first byte of control data (B23 to B16, i.e. the WM8599 register address). The WM8599 then acknowledges the first data byte by pulling SDIN low for one SCLK pulse. The controller then sends a second byte of control data (B15 to B8, i.e. the first 8 bits of register data), and the WM8599 acknowledges again by pulling SDIN low for one SCLK pulse. Finally, the controller sends a third byte of control data (B7 to B0, i.e. the final 8 bits of register data), and the WM8599 acknowledges again by pulling SDIN low for one SCLK pulse. |
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