WM8599SEFTSLASHV datasheet(19/74 Pages) WOLFSON

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WM8599

PP Rev 1.0 January 2007

SLAVE MODE

In slave mode, the master clock to left/right clock ratio can be auto-detected or set manually by

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DAC1_CTRL2

03h

2:0

DAC1_

SR[2:0]

000

DAC2_CTRL2

08h

2:0

DAC2_

SR[2:0]

000

DAC MCLK:LRCLK Ratio

000 = Auto detect

001 = 128fs

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = 1152fs

DAC1_SR[2:0] and DAC2_SR[2:0] should

always be set to the same value.

R14

ADC_CTRL2

0Eh

2:0

ADC_

SR[2:0]

000

ADC MCLK:LRCLK Ratio

000 = Auto detect

001 = 128fs

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = Reserved

Figure 9 Slave Mode MCLK to LRCLK Ratio Control

DIGITAL AUDIO DATA SAMPLING RATES

In a typical digital audio system there is one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

master clock. The WM8599 uses independent master clocks for ADC and DACs. The external

master clocks can be applied directly to the ADCMCLK and DACMCLK input pins with no software

configuration necessary. In a system where there are a number of possible sources for the reference

clock, it is recommended that the clock source with the lowest jitter be used for the master clock to

optimise the performance of the WM8599.

In slave clocking mode the WM8599 has a master detection circuit that automatically determines the

relationship between the master clock frequency (ADCMCLK, DACMCLK) and the sampling rate

(ADCLRCLK, DACLRCLK), to within +/- 32 system clock periods. The master clocks must be

synchronised with the left/right clocks, although the device is tolerant of phase variations or jitter on

the master clocks.

The ADC supports master clock to sampling clock ratios of 256fs to 768fs and sampling rates of

32kHz to 96kHz, provided the internal signal processing of the ADC is programmed to operate at the

correct rate. The DACs support master clock to sampling clock ratios of 128fs to 1152fs and

sampling rates of 32kHz to 192kHz, provided the internal signal processing of the DACs is

programmed to operate at the correct rate.

Table 9 shows typical master clock frequencies and sampling rates supported by the WM8599 ADC.

Table 10 shows typical master clock frequencies and sampling rates supported by the WM8599

DACs.

WM8599SEFT/V Datasheet(PDF) 19 Page - Wolfson Microelectronics plc

WM8599SEFT/V Datasheet(HTML) 19 Page - Wolfson Microelectronics plc

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