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WM8599SEFT/V Datasheet(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8599SEFT/V Datasheet(HTML) 11 Page - Wolfson Microelectronics plc |
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11 / 74 page ![]() Product Preview WM8599 w PP Rev 1.0 January 2007 11 DIGITAL AUDIO INTERFACE TIMING – SLAVE MODE Figure 2 Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25˚C, Slave Mode, fs = 48kHz, ADCMCLK, DACMCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information ADCBCLK / DACBCLK cycle time tBCY 80 ns ADCBCLK / DACBCLK pulse width high tBCH 30 ns ADCBCLK / DACBCLK pulse width low tBCL 30 ns ADCBCLK / DACBCLK rise/fall times 5 ns ADCLRCLK / DACLRCLK set-up time to ADCBCLK / DACBCLK rising edge tLRSU 22 ns ADCLRCLK / DACLRCLK hold time from ADCBCLK / DACBCLK rising edge tLRH 25 ns ADCLRCLK / DACLRCLK rise/fall times 5 ns DIN1/2 hold time from DACBCLK rising edge tDH 25 ns DOUT propagation delay from BCLK falling edge tDD 16 ns Table 2 Audio Interface Timing |
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