WM8599SEFTSLASHV datasheet(16/74 Pages) WOLFSON

16 / 74 page

WM8599

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PP Rev 1.0 January 2007

The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.

After receiving a complete address and data sequence the WM8599 returns to the idle state and

waits for another start condition. If a start or stop condition is detected out of sequence at any point

during data transfer (i.e. SDIN changes while SCLK is high), the WM8599 reverts to the idle

condition.

The WM8599 device address is 34h (0110100).

Figure 5 2-wire Write Protocol

AUTO-INCREMENT REGISTER WRITE

It is possible to write to multiple consecutive registers using the auto-increment feature. When

AUTO_INC is set, the register write protocol follows the method shown in Figure 6. As with normal

while SCLK remains high, and all devices on the bus receive the device address.

When the WM8599 has acknowledged a correct address, the controller sends the first byte of control

data (A6 to A0, i.e. the WM8599 initial register address). The WM8599 then acknowledges the first

control data byte by pulling SDIN low for one SCLK pulse. The controller then sends a byte of

address to be written to, and waits for the next byte of register data. Subsequent bytes of register

data can be written to consecutive registers of the WM8599 without setting up the device and register

address.

The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.

Figure 6 2-Wire Auto-Increment Register Write

The WM8599 allows readback of all registers with data output on the bidirectional SDIN pin. The

protocol is similar to that used to write to the device. The controller will issue the device address

followed by a write bit, and the register index will then be passed to the WM8599.

At this point the controller will issue a repeated start condition and resend the device address along

with a read bit. The WM8599 will acknowledge this and the WM8599 will become a slave transmitter.

The WM8599 will place the data from the indexed register onto SDIN MSB first. When the controller

receives the first byte of data, it acknowledges it. When the controller receives the second and final

byte of data it will not acknowledge receipt of the data indicating that it will resume master transmitter

control of SDIN. The controller will then issue a stop command completing the read cycle.

WM8599SEFT/V Datasheet(PDF) 16 Page - Wolfson Microelectronics plc