WM8599SEFTSLASHV datasheet(65/74 Pages) WOLFSON

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WM8599

PP Rev 1.0 January 2007

Figure 46 R36 – PGA Control Register 3

Figure 47 R37 – ADC Input Clock Control Register

R36 (24h) – PGA Control Register 3 (PGA_CTRL3)

Bit #

Read

Write

N/A

PGA_UPD

N/A

Default

Bit #

Read

Write

N/A

PGA_SEL[2:0]

PGA_

SAFE_SW

Default

N/A = Not Applicable (no function implemented)

Function

Description

PGA_SAFE_SW

PGA Ramp Control Clock Source Mux Force Update

0 = Wait until clocks are safe before switching PGA clock source

1 = Force PGA clock source to change immediately

See page 33 for details of use.

PGA_SEL[2:0]

PGA Ramp Control Clock Source

000 = ADCLRCLK

001 = DACLRCLK

010 to 110 = reserved

111 = ADCLRCLK (when ADC is being used in master mode)

PGA_UPD

PGA Ramp Control Clock Source Mux Update

0 = Do not update PGA clock source

1 = Update clock source

R37 (25h) – ADC Input Clock Control Register (ADC_CLK)

Bit #

Read

Write

N/A

Default

Bit #

Read

Write

N/A

ADC_

SAFE_SW

Default

N/A = Not Applicable (no function implemented)

Function

Description

ADC_SAFE_SW

ADC Clock Input Safe Switching

0 = Ignore ADC Clock Inputs

1 = Use ADC Clock Inputs

See page 29 for details of use

WM8599SEFT/V Datasheet(PDF) 65 Page - Wolfson Microelectronics plc

WM8599SEFT/V Datasheet(HTML) 65 Page - Wolfson Microelectronics plc

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