WM8599SEFTSLASHV datasheet(18/74 Pages) WOLFSON

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WM8599

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PP Rev 1.0 January 2007

DIGITAL AUDIO INTERFACE

Digital audio data is transferred to and from the WM8599 via the digital audio interface. The DACs

have independent data inputs with shared master clock, bit clock and left/right frame clock, and

operate in slave mode The ADC has independent master clock, bit clock and left/right frame clock in

addition to its data output, and can operate in both master and slave modes.

MASTER MODE

The ADC audio interface requires both a left/right frame clock (ADCLRCLK) and a bit clock

(ADCBCLK). These can be supplied externally (slave mode) or they can be generated internally

(master mode). Selection of master and slave mode is achieved by setting ADC_MSTR in ADC

Control Register 3 (R15).

The frequency of ADCLRCLK in master mode is dependent upon the ADC master clock frequency

and the ADC_SR[2:0] bits.

The frequency of ADCBCLK in master mode can be selected by ADC_BCLKDIV[1:0].

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

ADC_

SR[2:0]

000

ADC MCLK:LRCLK Ratio

000 = Auto detect

001 = 128fs

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = Reserved

R14

ADC_CTRL2

0Eh

5:3

ADC_BCLK

DIV[2:0]

000

ADC BCLK Rate

000 = MCLK / 4

001 = MCLK / 8

010 = 32fs

011 = 64fs

100 = 128fs

All other values of ADC_BCLKDIV[2:0] are

reserved

R15

ADC_CTRL3

0Fh

ADC_

MSTR

ADC Master Mode Select

0 = Slave mode, ADCBCLK and ADCLRCLK

are inputs to WM8599

1 = Master mode, ADCBCLK and

ADCLRCLK are outputs from WM8599

Table 8 ADC Master Mode Control

WM8599SEFT/V Datasheet(PDF) 18 Page - Wolfson Microelectronics plc

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