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3.2 Power Considerations

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

The C6421 provides several means of managing power consumption.

As described in the Section 6.3.4, C6421 Power and Clock Domains, the C6421 has one single power

domain—the “Always On” power domain. Within this power domain, the C6421 utilizes local clock gating

via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the PSC, see

Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320C642x Power and Sleep Controller

(PSC) User's Guide (literature number SPRUEN8).

Some of the C6421 peripherals support additional power saving features. For more details on power

saving features supported, see the TMS320C642x Peripherals Overview Reference Guide (literature

number SPRUEM3).

Most C6421 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN

For independent control, the 3.3-V I/Os are separated into functional groups—most of which are named

according to the pin multiplexing groups (see Table 3-2). For these I/O groups, only the I/O buffers needed

for Host/EMIFA Boot or Power-Up Operations are powered up by default (CLKOUT Block, EMIFA Block,

Host Block, and GPIO Block).

Note: To save power, all other I/O buffers are powered down by default. Before using these pins, the user

must program the VDD3P3V_PWDN register to power up the corresponding I/O buffers.

For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see

Section 3.7.3.1, Multiplexed Pins on C6421.

Note: The VDD3P3V_PWDN register only controls the power to the I/O buffers. The Power and Sleep

Controller (PSC) determines the clock/power state of the peripheral.

RESERVED

R-0000 0000 0000 0000

RESERVED

RSV

EMBK3

UR0FC

UR0DAT

TIMER1

TIMER0

PWM1

GPIO

HOST

EMBK2

EMBK1

EMBK0

CLKOUT

R-00

R/W-0

R/W-1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 3-1. VDD3P3V_PWDN Register

Table 3-2. VDD3P3V_PWDN Register Bit Descriptions

(1)

BIT

NAME

DESCRIPTION

31:14

RESERVED

Reserved. Read-only, writes have no effect.

Reserved. For proper device operation, this bit should be programmed to "1" during device

RSV

initialization (see Section 3.8, Device Initialization Sequence After Reset).

EMIFA Sub-Block 3 I/O Power Down Control.

Controls the power of the 8 I/O pins in the EMIFA Sub-Block 3.

EMBK3

0 = I/O pins powered up [default].

1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).

UART0 Flow Control Block I/O Power Down Control.

Controls the power of the 2 I/O pins in the UART0 Flow Control Block.

UR0FC

0 = I/O pins powered up.

1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].

(1)

For more details on I/O pins belonging to each pin mux block, see Section 3.7, Multiplexed Pin Configurations.

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