TMS320C6421 datasheet(87/227 Pages) TI

87 / 227 page

www.ti.com

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 3-17. PINMUX0 Register Bit Descriptions

Bit

Field Name

Description

Pins Controlled

Reserved. For proper device operation, the user should only write "0" to this bit

31:11

RESERVED

(default).

Sub-Block 1

Chip Select 3 Select.

EM_CS3/GP[13]

CS3SEL

0 = GPIO pin GP[13] (default)

The PINMUX0 field CS3SEL alone controls the

1 = EMIFA Chip Select 3 (EM_CS3)

muxing of this pin.

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

(default).

Chip Select 4 Select.

Sub-Block 1

0 = GPIO pin GP[32] (default) or RMII RMRXD0. Pin function determined by

RMRXD0/EM_CS4/GP[32]

CS4SEL

PINMUX0.RMII.

The combination of PINMUX0 fields CS4SEL

1 = EMIFA Chip Select 4 (EM_CS4). PINMUX0.RMII must be set to 0.

and RMII controls the muxing of this pin.

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

(default).

Chip Select 5 Select.

Sub-Block 1

0 = GPIO pin GP[33] (default) or RMII RMRXD1. Pin function determined by

RMRXD1/EM_CS5/GP[33]

CS5SEL

PINMUX0.RMII.

The combination of PINMUX0 fields CS5SEL

1 = EMIFA Chip Select 5 (EM_CS5). PINMUX0.RMII must be set to 0.

and RMII controls the muxing of this pin.

Reserved. For proper device operation, the user should only write "0" to this bit

5:4

RESERVED

(default).

RMII Select.

0 = No RMII in EMIFA Block

RMRXER/GP[52]

Field CS5SEL determines function of pin EM_CS5.

RMRXD1/EM_CS5/GP[33]

Field CS4SEL determines function of pin EM_CS4.

RMRXD0/EM_CS4/GP[32]

The remaining 6 pins function as GP[52] and GP[31:27].

REFCLK/GP[31]

RMCRSDV/GP[30]

1 = RMII in EMIFA Block

RMTXEN/GP[29]

RMII

These 8 pins function as RMII pins: RMRXER, RMRXD1, RMRXD0, REFCLK,

RMTXD0/GP[28]

RMCRSDV, RMTXEN, RMTXD0, and RMTXD1.

RMTXD1/GP[27]

When EMAC (RMII) is selected, EMAC(MII) must not be selected.

PINMUX1.HOSTBK must not be set to 011b or 100b.

The pin mux for these pins are controlled by a

CS4SEL and CS5SEL must be programmed to 0.

combination of PINMUX0 fields RMII, CS4SEL,

and CS5SEL.

If EMAC operation is desired, EMAC must be placed in reset before

programming PINMUX0.RMII or PINMUX1.HOSTBK to select EMAC pins.

Submit Documentation Feedback

Device Configurations

TMS320C6421 Datasheet(PDF) 87 Page - Texas Instruments

TMS320C6421 Datasheet(HTML) 87 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL