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TMS320C6421 Datasheet(PDF) 91 Page - Texas Instruments |
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TMS320C6421 Datasheet(HTML) 91 Page - Texas Instruments |
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91 / 227 page  www.ti.com 3.7.3 Pin Multiplexing Details TMS320C6421 Fixed-Point Digital Signal Processor SPRS346B – JANUARY 2007 – REVISED APRIL 2007 This section discusses how to program each Pin Mux Block to select the desired peripheral functions. The following steps can be used to determine pin muxing suitable for the application: 1. Understand the major configuration choices available for the specific application. a. Device Major Configuration Choices: Figure 3-10 shown in Section 3.7, Multiplexed Pin Configurations, provides a high-level view of the device pin muxing and can be used to determine the possible mix of peripheral options for a specific application. b. EMIFA Block Major Configuration Choices: The EMIFA block features extensive pin multiplexing to accommodate a variety of applications. In addition to Figure 3-10, Section 3.7.3.11, EMIFA Block Muxing, provides more details on the Major Configuration choices for this block. 2. See Section 3.7.3.1, Multiplexed Pins on C6421, for a summary of all the multiplexed pins on this device and the pin mux group they belong to. 3. Refer to the individual pin mux sections (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11, EMIFA Block Muxing) for pin muxing details for a specific pin mux block. a. For peripherals that span multiple pin mux blocks, the user must select the appropriate pins for that peripheral in all relevant pin mux blocks. For more details, see Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks . For details on PINMUX0 and PINMUX1 registers, see Section 3.7.2. 3.7.3.1 Multiplexed Pins on C6421 Table 3-19 summarizes all of the multiplexed pins on C6421, the pin mux group for each pin, and the PINMUX register fields that control the pin. For pin mux details, see the specific pin mux group section (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11, EMIFA Block Muxing). For a description of the PINMUX register fields, see Section 3.7.2. Table 3-19. Multiplexed Pins on C6421 SIGNAL PINMUX DESCRIPTION ZWT ZDU NAME PINMUX GROUP CONTROLLED BY PINMUX BIT FIELDS NO. NO. GP[54] A14 A18 EMIFA Sub-Block 0 - GP[53] A13 A17 EMIFA Sub-Block 0 - RMRXER/GP[52] A15 A19 EMIFA Sub-Block 0 RMII EM_A[13]/GP[51] B10 A12 EMIFA Sub-Block 0 AEM EM_A[14]/GP[50] A10 A13 EMIFA Sub-Block 0 AEM EM_A[15]/GP[49] B11 C13 EMIFASub-Block 0 AEM EM_A[16]/GP[48] C11 B13 EMIFA Sub-Block 0 AEM EM_A[17]/GP[47] A11 B14 EMIFASub-Block 0 AEM EM_A[18]/GP[46] D11 A14 EMIFA Sub-Block 0 AEM EM_A[19]/GP[45] B12 C14 EMIFASub-Block 0 AEM EM_A[20]/GP[44] C12 C15 EMIFA Sub-Block 0 AEM GP[43] A12 A15 EMIFA Sub-Block 0 GP[42] B13 B15 EMIFA Sub-Block 0 GP[41] C13 B16 EMIFA Sub-Block 0 GP[43:36] are standalone pins and are not GP[40] D14 C18 EMIFA Sub-Block 0 muxed with any other functions. They are included in this table because they are grouped GP[39] B14 A16 EMIFA Sub-Block 0 in the EMIFA Sub-Block 0. GP[38] C14 B17 EMIFA Sub-Block 0 GP[37] B15 B18 EMIFA Sub-Block 0 GP[36] C15 B19 EMIFA Sub-Block 0 EM_R/W/GP[35] D13 C17 EMIFA Sub-Block 0 AEM EM_A[21]/GP[34] D12 C16 EMIFA Sub-Block 0 AEM Submit Documentation Feedback Device Configurations 91 |
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