TMS320C6421 datasheet(96/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 3-21. Host Block Function Selection (continued)

PINMUX1

SETTING

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

HOSTBK

VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0], VLYNQ_TXD[3:0]

010

VLYNQ + GPIO (17)

GPIO: GP[83:67]

VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0], VLYNQ_TXD[3:0]

EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK,

RXD[3:0]

011

VLYNQ + EMAC (MII) + MDIO

MDIO: MDC, MDIO

If EMAC operation is desired, EMAC must be placed in reset before

programming PINMUX1.HOSTBK or PINMUX0.RMII to select EMAC pins.

EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK,

RXD[3:0]

MDIO: MDC, MDIO

100

EMAC (MII) + MDIO + GPIO (10)

GPIO: GP[66:57]

If EMAC operation is desired, EMAC must be placed in reset before

programming PINMUX1.HOSTBK or PINMUX0.RMII to select EMAC pins.

101 to 111

Reserved

The VDD3P3V_PWDN.HOST field determines the power state of the Host Block pins. The Host Block

pins default to powered up. For more details on the VDD3P3V_PWDN.HOST field, see Section 3.2, Power

Considerations.

3.7.3.4 UART0 Data Block Muxing

This block of 2 pins consists of UART0 Data, and GPIO muxed pins. The PINMUX1.UR0DBK register field

select the pin functions in the UART0 Data Block.

Table 3-22 summarizes the 2 pins in the UART0 Data Block, the multiplexed function on each pin, and the

PINMUX configurations to select the corresponding function.

Table 3-22. UART0 Data Block Muxed Pins Selection

MULTIPLEXED FUNCTIONS

SIGNAL

UART0

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

URXD0/GP[85]

URXD0

GP[85]

UR0DBK = 1

UR0DBK = 0

UTXD0/GP[86]

UTXD0

GP[86]

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span

across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0

operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two

pins in the UART0 Flow Control Block are optional.

Table 3-23 provides a different view of the UART0 Data Block pin muxing, showing the UART0 Data Block

function based on PINMUX1.UR0DBK setting. The selection options are also shown pictorially in

Figure 3-10.

Table 3-23. UART0 Data Block Function Selection

PINMUX1.UR0DBK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (2) (Default)

GPIO: GP[86:85]

UART0 Data

UART0: URXD0, UTXD0

Device Configurations

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