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3.7.1

Pin Muxing Selection At Reset

3.7.2

Pin Muxing Selection After Reset

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

This section summarizes pin mux selection at reset.

The configuration pins AEM[2:0] latched at device reset determine default pin muxing for the following Pin

Mux Blocks:

• EMIFA Block: default pin mux determined by AEM[2:0] and RMII. After reset, software may modify

settings in the PINMUX0 register to fine tune pin muxing in this block.

–

AEM[2:0] = 000b, RMII = 0: Major Config Option A is selected. This block defaults to 58 GPIO pins.

–

AEM[2:0] = 000b, RMII = 1: Major Config Option B is selected. This block defaults to EMAC(RMII),

plus 50 GPIO pins.

–

AEM[2:0] = 010b, RMII = 0: Major Config Option C is selected. This block defaults to 8-bit EMIFA

(Async) Pinout Mode 2, plus 13-to-16 GPIO pins.

–

AEM[2:0] = 010b, RMII = 1: Major Config Option D is selected. This block defaults to 8-bit EMIFA

(Async) Pinout Mode 2, EMAC(RMII), plus 7-to-8 GPIO pins.

–

AEM[2:0] = 101b, RMII = 0: Major Config Option E is selected. This block defaults to 8-bit EMIFA

(NAND) Pinout Mode 5, plus 44-to-47 GPIO pins.

–

AEM[2:0] = 101b, RMII = 1: Major Config Option F is selected. This block defaults to 8-bit EMIFA

(NAND) Pinout Mode 5, EMAC(RMII), and 38-to-39 GPIO pins.

For a description of the PINMUX0 and PINMUX1 registers and more details on pin muxing, see

Section 3.7.2.

The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions in

the Pin Mux Blocks. The pin control of some of the Pin Mux Blocks requires a combination of

PINMUX0/PINMUX1 bit fields. For more details on the combination of the PINMUX bit fields that control

each muxed pin, see Section 3.7.3.1, Multiplexed Pins on C6421.

This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed

discussion on how to program each Pin Mux Block, see Section 3.7.3, Pin Multiplexing Details.

3.7.2.1 PINMUX0 Register Description

The Pin Multiplexing 0 Register (PINMUX0) controls the pin function in the EMIFA Block. The PINMUX0

pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX bit fields that

control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on C6421. For more information on EMIFA

Block pin muxing, see Section 3.7.3.11, EMIFA Block Muxing. For the pin-by-pin muxing control of the

EMIFA Block, see Section 3.7.3.11.2, EMIFA Block Pin-By-Pin Multiplexing Summary.

RESERVED

R/W-0000 0000 0000 0XXX

RESERVED

CS3SEL

RSV

CS4SEL

RSV

CS5SEL

RESERVED

RMII

AEM

R/W-0000 0

R/W-0

R/W-00

R/W-0

R/W-LLL

LEGEND: R/W = Read/Write; R = Read only; L = pin state latched at reset rising edge; -n = value after reset

(1) For proper C6421 device operation, always write a value of "0" to all RESERVED/RSV bits.

(2) PINMUX0 bits 18:16 are reserved/ don't care. These bits may default to non-zero values.

Figure 3-11. PINMUX0 Register (1) (2)

Device Configurations

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