TMS320C6421 datasheet(97/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

In addition, the VDD3P3V_PWDN.UR0DAT field determines the power state of the UART0 Data Block

pins. The UART0 Data Block pins default to powered down and not operational. To use these pins, user

must first program VDD3P3V_PWDN.UR0DAT = 0 to power up the pins. For more details on the

VDD3P3V_PWDN.UR0DAT field, see Section 3.2, Power Considerations.

The UART0 Data Block features internal pullup resistors, which matches the UART inactive polarity.

3.7.3.5 UART0 Flow Control Block

This block of 2 pins consists of UART0 Flow Control, PWM0, and GPIO muxed pins. The

PINMUX1.UR0FCBK register field selects the pin functions in the UART0 Flow Control Block.

Table 3-24 summarizes the 2 pins in the UART0 Flow Control Block, the multiplexed function on each pin,

and the PINMUX configurations to select the corresponding function.

Table 3-24. UART0 Flow Control Block Muxed Pins Selection

MULTIPLEXED FUNCTIONS

SIGNAL

UART0

PWM0

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

UCTS0/

UCTS0

–

GP[87]

UR0FCBK = 00/10

GP[87]

UR0FCBK = 01

URTS0/

PWM0/

URTS0

PWM0

UR0FCBK = 10

GP[88]

UR0FCBK = 00

GP[88]

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span

across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0

operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two

pins in the UART0 Flow Control Block are optional.

Table 3-25 provides a different view of the UART0 Flow Control Block pin muxing, showing the UART0

Flow Control Block function based on PINMUX1.UR0FCBK setting. The selection options are also shown

pictorially in Figure 3-10.

Table 3-25. UART0 Flow Control Block Function Selection

PINMUX1.UR0FCBK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (2) (default)

GPIO: GP[88:87]

UART0 Flow Control

UART0: UCTS0, URTS0

PWM0: PWM0

PWM0 + GPIO (1)

GPIO: GP[87]

Reserved

In addition, the VDD3P3V_PWDN.UR0FC field determines the power state of the UART0 Flow Control

Block pins. The UART0 Flow Control Block pins default to powered down and not operational. To use

these pins, user must first program VDD3P3V_PWDN.UR0FC = 0 to power up the pins. For more details

on the VDD3P3V_PWDN.UR0FC field, see Section 3.2, Power Considerations.

The UART0 Flow Control Block features internal pullup resistors, which matches the UART inactive

polarity.

3.7.3.6 Timer0 Block

This block of 2 pins consists of Timer0 and McBSP0 muxed pins. The PINMUX1.TIM0BK register field

selects the pin functions in the Timer0 Block.

Table 3-26 summarizes the 2 pins in the Timer0 Block, the multiplexed function on each pin, and the

PINMUX configurations to select the corresponding function.

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