TMS320C6421 datasheet(70/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 3-4. Non-Fastboot Modes (FASTBOOT = 0)

DEVICE BOOT AND

CONFIGURATION

PLLC1 CLOCK SETTING AT BOOT

PINS

C6421 DSP

DSPBOOTADDR

BOOT DESCRIPTION(1)

(Master/Slave)

(DEFAULT)(1)

DEVICE

PLL

CLKDIV1 DOMAIN

BOOTMODE[3:0]

FREQUENCY

MODE(2)

(SYSCLK1 DIVIDER)

(SYSCLK1)

0000

No Boot (Emulation Boot)

Master

Bypass

CLKIN

0x0010 0000

0001

Reserved

–

0010

HPI Boot

Slave

Bypass

CLKIN

0x0010 0000

0011

Reserved

–

EMIFA ROM Direct Boot

0100

Master

Bypass

CLKIN

0x4200 000

[PLL Bypass Mode]

I2C Boot

0101

Master

Bypass

CLKIN

0x0010 0000

[STANDARD MODE](3)

0110

16-bit SPI Boot [McBSP0]

Master

Bypass

CLKIN

0x0010 0000

0111

NAND Flash Boot

Master

Bypass

CLKIN

0x0010 0000

UART Boot without

1000

Hardware Flow Control

Master

Bypass

CLKIN

0x0010 0000

[UART0]

1001

Reserved

–

1010

Reserved

–

1011

Reserved

–

1100

Reserved

–

1101

Reserved

–

UART Boot with Hardware

1110

Master

Bypass

CLKIN

0x0010 0000

Flow Control [UART0]

1111

Reserved

–

(1)

For all boot modes that default to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,

BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the

bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application code must explicitly enable the

cache. For more information on the bootloader, see the Using the TMS320C642x Bootloader Application Report (literature number

SPRAAK5).

(2)

The PLL MODE for Non-Fastboot Modes is fixed as shown in this table; therefore, the PLLMS[2:0] configuration pins have no effect on

the PLL MODE.

(3)

I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz and 30 MHz. I2C Boot is not

available for MXI/CLKIN frequencies less than 21 MHz.

Device Configurations

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