TMS320C6421 datasheet(79/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

3.5.1.1 EMIFA Pinout Mode (AEM[2:0])

To support different usage scenarios, the C6421 provides intricate pin multiplexing between the EMIFA

and other peripherals. The PINMUX0.AEM register bit field in the System Module determines the EMIFA

Pinout Mode. The AEM[2:0] pins only select the default EMIFA Pinout Mode. It is latched at device reset

de-assertion (high) into the BOOTCFG.DAEM bit field. The AEM[2:0] value also sets the default of the

PINMUX0.AEM bit field. While the BOOTCFG.DAEM bit field shows the actual latched value and cannot

be modified, the PINMUX0.AEM value can be changed by software to modify the EMIFA Pinout Mode.

Note: The AEM[2:0] value does not affect the operation of the EMIFA module itself. It only affects which

EMIFA pins are brought out to the device pins. For more details on the AEM settings, see Section 3.7,

Multiplexed Pin Configurations.

3.5.1.2 FASTBOOT PLL Multiplier Select (PLLMS)

If FASTBOOT = 1, the PLLMS[2:0] pins select PLL multiplier for Fastboot modes. If FASTBOOT = 0, the

PLLMS[2:0] pins are ignored.

The PLLMS[2:0] pin values are latched at device reset de-assertion into the BOOTCFG.PLLMS field and

cannot be modified by software. This value is only applicable during fast boot.

For more information on boot modes and the FASTBOOT PLL multiplier selection, see Section 3.4.1, Boot

Modes.

3.5.1.3 Endianess Selection (LENDIAN)

The LENDIAN configuration pin latched at reset determines the endianess setting of the device. If

LENDIAN = 1, little endian is selected. If LENDIAN = 0, big endian is selected.

The setting is latched and stored in the BOOTCFG.LENDIAN field and cannot be modified by software.

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Device Configurations

TMS320C6421 Datasheet(PDF) 79 Page - Texas Instruments