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TMS320C6421 Datasheet(PDF) 92 Page - Texas Instruments |
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TMS320C6421 Datasheet(HTML) 92 Page - Texas Instruments |
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92 / 227 page  www.ti.com TMS320C6421 Fixed-Point Digital Signal Processor SPRS346B – JANUARY 2007 – REVISED APRIL 2007 Table 3-19. Multiplexed Pins on C6421 (continued) SIGNAL PINMUX DESCRIPTION ZWT ZDU NAME PINMUX GROUP CONTROLLED BY PINMUX BIT FIELDS NO. NO. RMRXD1/EM_CS5/GP[33] F19 J22 EMIFA Sub-Block 1 RMII, CS5SEL RMRXD0/EM_CS4/GP[32] E19 H22 EMIFA Sub-Block 1 RMII, CS4SEL REFCLK/GP[31] D19 G22 EMIFA Sub-Block 1 RMII RMCRSDV/GP[30] G19 K22 EMIFA Sub-Block 1 RMII RMTXEN/GP[29] H15 K21 EMIFA Sub-Block 1 RMII RMTXD0/GP[28] H16 J21 EMIFA Sub-Block 1 RMII RMTXD1/GP[27] H17 L19 EMIFA Sub-Block 1 RMII GP[26]/(FASTBOOT) G17 K19 EMIFA Sub-Block 1 - GP[25]/(BOOTMODE3) G16 H21 EMIFA Sub-Block 1 - GP[24]/(BOOTMODE2) G15 L20 EMIFA Sub-Block 1 - GP[23]/(BOOTMODE1) F15 K20 EMIFA Sub-Block 1 - GP[22]/(BOOTMODE0) F18 J20 EMIFA Sub-Block 1 - EM_D[7]/GP[21] F17 H20 EMIFA Sub-Block 1 AEM EM_D[6]/GP[20] F16 F21 EMIFA Sub-Block 1 AEM EM_D[5]/GP[19] E17 F22 EMIFA Sub-Block 1 AEM EM_D[4]/GP[18] E18 G21 EMIFA Sub-Block 1 AEM EM_D[3]/GP[17] E16 F20 EMIFA Sub-Block 1 AEM EM_D[2]/GP[16] D17 E22 EMIFA Sub-Block 1 AEM EM_D[1]/GP[15] D18 G20 EMIFA Sub-Block 1 AEM EM_D[0]/GP[14] D16 E21 EMIFA Sub-Block 1 AEM EM_CS3/GP[13] C18 D22 EMIFA Sub-Block 1 CS3SEL EM_CS2/GP[12] C19 C22 EMIFA Sub-Block 1 AEM EM_A[3]/GP[11] B18 D21 EMIFA Sub-Block 1 AEM EM_A[4]/GP[10]/(PLLMS2) A17 B21 EMIFA Sub-Block 1 AEM EM_A[1]/(ALE)/GP[9]/(PLLMS1) A16 B20 EMIFA Sub-Block 1 AEM EM_A[2]/(CLE)/GP[8]/(PLLMS0) B16 A20 EMIFA Sub-Block 1 AEM EM_A[0]/GP[7]/(AEM2) B17 C21 EMIFA Sub-Block 1 AEM EM_BA[0]/GP[6]/(AEM1) C17 E20 EMIFA Sub-Block 1 AEM EM_BA[1]/GP[5]/(AEM0) C16 C20 EMIFA Sub-Block 1 AEM EM_A[12]/GP[89] D10 B12 EMIFA Sub-Block 3 AEM EM_A[11]/GP[90] C10 C12 EMIFA Sub-Block 3 AEM EM_A[10]/GP[91] A9 B11 EMIFA Sub-Block 3 AEM EM_A[9]/GP[92] D9 C11 EMIFA Sub-Block 3 AEM EM_A[8]/GP[93] B9 A11 EMIFA Sub-Block 3 AEM EM_A[7]/GP[94] C9 C10 EMIFA Sub-Block 3 AEM EM_A[6]/GP[95] D8 B10 EMIFA Sub-Block 3 AEM EM_A[5]/GP[96] B8 A10 EMIFA Sub-Block 3 AEM VLYNQ_CLOCK/GP[57] A7 A8 Host Block HOSTBK HD0/VLYNQ_SCRUN/GP[58] C8 B9 Host Block HOSTBK HD1/VLYNQ_RXD0/GP[59] D7 C9 Host Block HOSTBK HD2/VLYNQ_RXD1/GP[60] A8 A9 Host Block HOSTBK HD3/VLYNQ_RXD2/GP[61] B7 B8 Host Block HOSTBK HD4/VLYNQ_RXD3/GP[62] C7 C8 Host Block HOSTBK HD5/VLYNQ_TXD0/GP[63] A6 A7 Host Block HOSTBK HD6/VLYNQ_TXD1/GP[64] D6 C7 Host Block HOSTBK HD7/VLYNQ_TXD2/GP[65] B6 B7 Host Block HOSTBK HD8/VLYNQ_TXD3/GP[66] A5 A6 Host Block HOSTBK HD9/MCOL/GP[67] C6 C6 Host Block HOSTBK HD10/MCRS/GP[68] B5 B6 Host Block HOSTBK Device Configurations 92 Submit Documentation Feedback |
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