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3.3 Clock Considerations

3.3.1

Clock Configurations after Device Reset

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and

the Power and Sleep Controller (PSC).

After device reset, the user is responsible for programming the PLL Controllers (PLLC1 and PLLC2) and

the Power and Sleep Controller (PSC) to bring the device up to the desired clock frequency and the

desired peripheral clock state (clock gating or not).

For additional power savings, some of the C6421 peripherals support clock gating within the peripheral

boundary. For more details on clock gating and power saving features supported by a specific peripheral,

see the TMS320C642x Peripherals Overview Reference Guide (literature number SPRUEM3).

3.3.1.1 Device Clock Frequency

The C6421 defaults to PLL bypass mode. To bring the device up to the desired clock frequency, the user

should program PLLC1 and PLLC2 after device reset.

C6421 supports a FASTBOOT option, where upon exit from device reset the internal bootloader code

automatically programs the PLLC1 into PLL mode with a specific PLL multiplier and divider to speed up

device boot. While the FASTBOOT option is beneficial for faster boot, the PLL multiplier and divider

selected for boot may not be the exact frequency desired for the run-time application. It is the user's

responsibility to reconfigure PLLC1 after fastboot to bring the device into the desired clock frequency.

Section 3.4.1, Boot Modes, discusses the different fast boot modes in more detail.

The user must adhere to the various clock requirements when programming the PLLC1 and PLLC2:

• Fixed frequency ratio requirements between CLKDIV1, CLKDIV3, and CLKDIV6 clock domains. For

more details on the frequency ratio requirements, see Section 6.3.4, C6421 Power and Clock

Domains.

• PLL multiplier and frequency ranges. For more details on PLL multiplier and frequency ranges, see

Section 6.7.1, PLL1 and PLL2.

3.3.1.2 Module Clock State

The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC).

Table 3-3 shows the default state of each module after a device-level global reset. The C6421 device has

four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on the

definitions of the module states, the PSC, and PSC programming, see Section 6.3.5, Power and Sleep

Controller (PSC) and the TMS320C642x Power and Sleep Controller (PSC) User's Guide (literature

number SPRUEN8).

Table 3-3. C6421 Default Module States

DEFAULT MODULE STATE

LPSC #

MODULE NAME

[PSC Register MDSTATn.STATE]

EDMACC

SwRstDisable

EDMATC0

SwRstDisable

EDMATC1

SwRstDisable

EDMATC2

SwRstDisable

EMAC Memory Controller

SwRstDisable

MDIO

SwRstDisable

EMAC

SwRstDisable

McASP0

SwRstDisable

VLYNQ

SwRstDisable

HPI

SwRstDisable

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Device Configurations

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