Analog Integrated Circuit Device Data

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30

Freescale Semiconductor

34844

TYPICAL APPLICATIONS

LAYOUT GUIDELINES

LAYOUT GUIDELINES

RECOMMENDED STACK-UP

Table 9 shows the recommended layer stack-up for the signals to have good shielding and Thermal Dissipation.

DECOUPLING CAPS

It is recommended to place decoupling caps of 100 pf at the beginning and at the end of any power signal traces to filter high frequency

noise. Decoupling caps of 100 pf should also be placed at the end of any long trace to cancel antenna effects. These caps should be

located as closed as possible to the point to be decoupled and the connection to GND should be as short as possible.

SM-BUS/I2C COMMUNICATION AND CLOCK SIGNALS (SDA, SCK AND CK)

To avoid contamination of these signals by nearby high power or high frequency signals, it is a good practice to shield them with ground

planes placed on adjacent layers. Make sure the ground plane is uniform through the whole signal trace length.

Figure 12. Recommended shielding for critical signals.

These signals should not run parallel to power signals or other clock signals in the same routing layer. If they have to cross or to be

routed close to a power signal, it is a good practice to trace them perpendicularly or at 45° on a different layer to avoid coupling noise.

SWITCHING NODE (SWA & SWB)

The components associated to this node must be placed as close as possible to each other to keep the switching loop small enough

so it does not contaminate other signals. However, care must be taken to ensure the copper traces used to connect these components

together on this node, and are capable of handling the necessary current and voltage.

As a reference, a 10 mils trace with a thickness of 1.0 oz. of copper is capable of handling one ampere.

Traces for connecting the inductor, input and output caps should be as wide and short as possible to avoid adding inductance or

resistance to the loop. The placement of these components should be selected far away from sensitive signals like compensation,

feedback, and internal regulators to avoid power noise coupling.

COMPENSATION COMPONENTS

Components related with COMP pin need to be placed as close as possible to the pin.

FEEDBACK SIGNAL

The trace of the feedback signal (VOUT) should be routed perpendicularly or at 45° on a different layer to avoid coupling noise,

preferably between ground or power planes.

Table 9. Layer Stacking Recommendations

Stack-Up

Layer 1 (Top)

Signal

Layer 2 (Inner 1)

Ground

Layer 3(Inner 2)

Signal

Layer 4 (Bottom)

Ground

Signal

Ground Plane

Ground Planes

Signal

DO